07-13-2018 07:21 AM
I have a FIFO with the following settings:
Native, Independent Clocks Builtin FIFO
Write Width : 32
Write Depth : 512
Read Clock Frequency : 100 MHz
Write Clock Frequency : 148 MHz
The rest of the setting are by default.
I am suing this FIFO to write a single 32 bit word, and as soon as Empty Flags goes low , i am reading the word.
Most of the time everything is ok , but sometimes i have the following situation.
At one point i am writing into the fifo. I can see that Empy flag is still high. When it becomes low and i am assigning FifoRdReq i am getting two words. I don't understand why this happens ?
07-18-2018 01:43 AM
Based on FIFO Generator v13.1 LogiCORE IP Product Guide (PG057) in order to avoid this issue i decided to use Valid flag.So i assign FifoRdReq for one clock cycle when based on the Empty flag going low and when Valid flag is high read the correct data from the FIFO.