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Visitor
2,025 Views
Registered: ‎05-16-2018

## Fifo write depth

I am working on a project that needs to store data on a FIFO. The write clock used is 200MHz and the read clock is 100MHz. The input is 16 bit wide. I want to know what should be the write depth and how to do I know that should be the depth.

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Highlighted
Scholar
1,950 Views
Registered: ‎06-21-2017

@dawnfrank

The average rate that you read out of the FIFO must, in the long run, be equal to the rate you are writing into it.  You can use the FIFO empty flag to ensure that you are not reading too fast.  If you are writing one 16-bit word every 5 nS, you must read out 2*200 = 400 million bytes per second.  As @dpaul24 mentioned, you can make your read width wider than the write width, enabling you to read out more bytes on every 100MHz clock.  Just a word of caution, if your 200MHz and 100MHz clocks are not phase coherent, that is if they do not trace back to the same oscillator, you can't count on the 200MHz clock being exactly twice the frequency of the 100MHz clock.

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Moderator
2,011 Views
Registered: ‎08-08-2017

Is Writing and reading from FIFO is continuous (wr_en and rd_en = '1') or controlled by wr_en and rd_en signals ?

What is the no of words to be transferred from 200MHz clock domain to 100MHz Clock Domain?

Consider the No of words  = x

Wr_clk = 200MHz

Rd_clk = 100 MHz

Time required to write 1 word = 1/200 = 5 ns

Time required to read 1 word = 1/100 = 10 ns

Time required to write X words  =   5x    ns

Time required to read X word    =    10x    ns

And the no. of words can be read in a duration of  5x ns  =  5x/10 =  0.5x

The remaining no. of words to be stored in the FIFO = x – 0.5x = 0.5x.

So the FIFO should be capable of storing (or Write depth) minimum of 0.5x  words.

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Highlighted
Visitor
1,999 Views
Registered: ‎05-16-2018

It is controlled by the wr_en and rd_en signals. The number of words to be transferred from 200MHz domain to 100Mhz domain is 1 at a time.  Sorry I'm just a beginner.  I just want to make sure the FIFO doesn't fill entirely. So what should be the write depth in that situation?

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Moderator
1,993 Views
Registered: ‎08-08-2017

I mean How many Data words are received from upstream device (Transmitter)?

Lets say if you are receiving "X" 16 bit words then above logic is applicable.

If you just want to transfer one word from 200MHz to 100Mhz then you can use XPM_CDC_Gray (Synchronization via Gray coding)

Refer to page 13 of User guide  (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug974-vivado-ultrascale-libraries.pdf)

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Highlighted
Visitor
1,980 Views
Registered: ‎05-16-2018

The data comes from a sensor. So it is received continuously. I just want to store them and use it for some processing.

Highlighted
Scholar
1,975 Views
Registered: ‎08-07-2014

The input is 16 bit wide. I want to know what should be the write depth and how to do I know that should be the depth.

Also important to know what is the read width. Is it also 16bits?

Because this also affects the fifo depth.

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FPGA enthusiast!
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Highlighted
Scholar
1,959 Views
Registered: ‎06-21-2017

If you are receiving data continuously on a 200MHz clock, you cannot read it out fast enough with a 100MHz clock to avoid overflowing your FIFO, no matter how deep it is.

Highlighted
Visitor
1,935 Views
Registered: ‎05-16-2018

@dpaul24

Yes the read width is also 16 bit.

@bruce_karaffa

If so, could you tell how can data be moved from a higher clock domain to a slower one without losing the data? Is there any rule or method or something that must be followed to ensure the FIFO doesn't get overflown?

Thank you all for your help, :).

Highlighted
Scholar
1,930 Views
Registered: ‎08-07-2014

Then bruce_karaffa comment is valid.

You can go for an asymmetric FIFO. Reading a larger size word may help.

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FPGA enthusiast!