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mgdudhat
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Registered: ‎09-15-2019

Full Duplex Aurora : no Lane up and channel up for Aurora 8B/10B XIlinx IP

hi guys,

i am using xilinx Aurora 8B/10B IP for the high speed serial transmission (Lina rate : 4.6875Gbps, Ref Clk: 312.5MHz )  from one PCB with other PCB having the same Aurora IP with same configuration and pin assignments for TX, RX and REfclk also seems ok. I have also analysed all required status signals of Aurora IP uisng ILA core and and it shows me the results as attached. The valus shown is 0x682 that is as follows for the signals:

Bit   ->              10                              9           8                 7                                   6                                  5            4                 3                  2                   1                                    0

Signal-> tx_resetdone_out    tx_lock     soft_err      rx_reset_done_out   pll_not_locked_out            lane_up     hard_err    frame_err    crc_valid     crc_pass_fail_in            channel_up

value(0x682) -->              1               1             0              1                                     0                                 0             0                    0                0                    1                                0

so from above result : lane_up (bit5) and channel_up(bit0) is zero.

I have attcahed also view of aurora ip block diagram.

let me know your suggstions for this.

Many thanks in advance.

 

10_09_ila_view_1.PNG
16_09_aurora_ila_axi_gpio_core.PNG
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tedbooth
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Registered: ‎03-28-2016

@mgdudhat 

I would suggest that you look into the "loopback" capabilities of the Aurora IP.  See if you can establish "Lane Up" and "Channel Up" when using one of the on-chip loopback modes.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
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