08-24-2020 08:13 AM
Does anyone know how to set initial data values in a BRAM, instantiated in a block diagram, that is connected to an AXI BRAM Controller, for simulation? COE files can't be used if the BRAM is in BRAM Controller mode. Xilinx literature states that it can be done using MEM files but I can’t find anywhere that explains how. I can write a MEM file but can’t find out what to do with it after that.
The BMG Documentation specifically calls it out (Block Memory Generator v8.3, pg 10):
“The memory contents can be optionally initialized using a memory coefficient (COE) file or by using the default data option. A COE file can define the initial contents of each individual memory location, while the default data option defines the initial content of all locations.
Note: When using IP integrator, the initialization in BRAM Controller Mode is done only through the MEM file. For more details, see Update MEM to Update Bit Files with MMI and ELF Data in Embedded Processor Hardware Design User Guide (UG898)”
User Guide 898 has this to say on page 161:
“The Vivado Design Suite also supports a MEM File format for memory initialization as describedat this link in the Vivado Design Suite User Guide: Synthesis (UG901). The MEM File format supported by the Vivado Design Suite is different from the file format supported by UpdateMEM.”
User Guide 901 is a dead end however, and makes no reference to MEM files. Page 152 begins the section on initializing RAM contents, but the approaches are to either initialize it in the source code for the HDL you wrote yourself (not applicable) or to write an HDL procedure to load the ram though its ports on simulation start, which is clunky and seems like entirely too much effort to go to for the several RAMs in this system, which don’t already have their write ports exposed to logic.
I’m using Vivado 2019.2 and have used the Block Memory Generator to instantiate a true dual port RAM in the block diagram. One port is tied to an AXI BRAM Controller and the other port is pushed external to the block diagram to connect to the rest of the system. A BRAM can be initialized with a COE file so long as it is either 1) on the block diagram but not connected to an AXI controller or 2) instantiated outside of a block diagram and connected to an AXI controller on the diagram through the diagram’s ports. In either one of these situations the “Load COE File” option in the IP Configuration dialog is not greyed out and works – in simulation the BRAM holds the values specified in the COE file. An obvious solution is to move the BRAM off the block diagram as in option 2, but this is less elegant for a number of reasons and Xilinx keeps hinting at the tantalizing MEM file solution.
10-13-2020 03:32 PM
Until Xilinx responds or corrects their documentation it looks like MEM file usage will remain a mystery.
However, I can happily report that when using a Block Memory Generator BRAM with an AXI BRAM Controller, the BRAM doesn't have to be in BRAM Controller Mode. While I didn't see this explicitly mentioned in the documentation, I switched the BRAM to Standalone mode and was able to successfully initialize it with a COE file for simulation purposes. In Standalone mode the Address Editor and the BRAM IP Customization are no longer linked, so the Range & Write Depth fields, respectively, will need to be manually aligned.