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h4cks4w
Observer
Observer
11,365 Views
Registered: ‎08-16-2013

How can I natively instantiate a fifo_generator FIFO in Verilog?

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Around two years ago, I used to be able to instantiate fifo_generator FIFOs in Verilog like so:

 

fifo_generator_v10_0
#(
// Parameters go here
)
fifo_generator
(
// Port connections go here
);

When I synthesized this with Vivado, I would take this file:

 

${VIVADO_ROOTDIR}/data/ip/xilinx/fifo_generator_v10_0/analyze_order.txt

 

And run Tcl commands that looked like this:

# Run once per file in analyze_order.txt where $order_file is the file name
set_property library $order_lib [add_files {$order_file}

 

I've installed Vivado 2015.4 now and see that the analyze_order.txt files no longer exist with the latest versions of fifo_generator (v12_0 and v13_0).  I first tried to instantiate fifo_generator_v12_0 and then included all the encrypted VHDL in ${VIVADO_ROOTDIR}/data/ip/xilinx/fifo_generator_v12_0/hdl.  This resulted in a "module not found" error message.  I then built a FIFO with the IP Generator GUI (which, of course, I can synthesize) and found that the hierarchy viewer shows a fifo_generator_v13_0_1 down in there.  I tried to instantiate this (with and without the trailing '_1') and still got the "module not found" error message.

 

Does anyone know how to instantiate v12_0 or v13_0 fifo_generator FIFOs in Verilog?

 

Also, I realize this question is similar to this thread:

https://forums.xilinx.com/t5/Synthesis/FIFO-generator-instantiation-without-CORE-Generator/m-p/217041#M5834

However, the world seems to have moved on.  As noted above, I don't believe this works anymore.

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vemulad
Xilinx Employee
Xilinx Employee
19,907 Views
Registered: ‎09-20-2012

Hi @h4cks4w

 

You need to add block memory generator files too. 

 

The library of the files also needs to be set correctly. I have attached a sample 2015.4 project here. Hope this helps.

Thanks,
Deepika.
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4 Replies
vemulad
Xilinx Employee
Xilinx Employee
19,908 Views
Registered: ‎09-20-2012

Hi @h4cks4w

 

You need to add block memory generator files too. 

 

The library of the files also needs to be set correctly. I have attached a sample 2015.4 project here. Hope this helps.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

h4cks4w
Observer
Observer
11,318 Views
Registered: ‎08-16-2013

@vemulad, thanks for the response.  You were right that I didn't have the library set correctly for the fifo_generator sources I was pulling in.  I copied what you had in the example project and now I can synthesize the FIFO.  When I try to implement this design, I now get errors about the blk_mem_gen (which you also predicted):

[Project 1-486] Could not resolve non-primitive black box cell 'blk_mem_gen_v8_3_1' instantiated as 'fifo/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg' ["/tools/xilinx/Vivado/2015.4/Vivado/2015.4/data/ip/xilinx/fifo_generator_v13_0/hdl/fifo_generator_v13_0_vhsyn_rfs.vhd":1]
[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'fifo/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg' of type 'fifo/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_gen_v8_3_1' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.

I then added these files:

blk_mem_gen_v8_3.vhd  blk_mem_gen_v8_3_vhsyn_rfs.vhd

from here:

data/ip/xilinx/blk_mem_gen_v8_3/hdl/

 

I tried both putting them in both blk_mem_gen_v8_3_1 and fifo_generator_v13_0_1 libraries, but I'm still getting the black box errors.  How can I tell what library Vivado wants the blk_mem_gen to be in?

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vemulad
Xilinx Employee
Xilinx Employee
11,138 Views
Registered: ‎09-20-2012

Hi @h4cks4w

 

Did you add the files to correct libraries as shown in my sample project which I uploaded in my earlier post? Below is the snapshot for your reference.

 

Capture.PNG

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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h4cks4w
Observer
Observer
11,109 Views
Registered: ‎08-16-2013

Face -> palm.  Sorry, I'm not in the IDE that often and was not familiar with this Libraries tab.  Now that I copied exactly what you have, it's working for me.

 

Thanks for the help, @vemulad.

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