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katrenoopur
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Visitor
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Registered: ‎12-02-2020

How to add one clock cycle read latency in vhdl

M using single port BRAM in always enabled mode, when I want to read the data from BRAM and write into the 2D array , its shows 1 clock cycle read latency means the data is not exact, after adding output register to the BRAM it shows 2 clocks cycle latency. Kindly suggest me,how to remove this. I am using VHDL.

I cant use flipflops and multiplexers, BRAM is required, I already instantiate the BRAM with coe file and now only wants to read one address at a time then fill into the array then again read the next address of BRAM and write into the array and so on. Is there any way to provide the delay in the logic itself? I am using Xilinx ISE, IP core generator for BRAM.

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pthakare
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Registered: ‎08-08-2017

Hi @katrenoopur 

I am not very sure if i understand your query correctly but wanted to add on latency

The The core supports embedded block RAM registers as well as registers implemented in the FPGA general interconnect.

These are primitive output register and core output register settings in IP.  Core output register is implemented in the FPGA general interconnect .

pthakare_0-1608214053087.png

 

Read latency 1 corresponds to use of memory latch only; 2 causes use of embedded output register if selected in IP.

3 causes use of core  output register selected in IP.  You can also have read latency 2 bypassing embedded output register and used core output register.

So wondering what is your exact requirement here.

 

 

 

 

 

 

 

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bruce_karaffa
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Registered: ‎06-21-2017

You need to supply the address to the BRAM several clock cycles before you write it to your array.  How many clock cycles the address needs to be ahead of the data depends on whether you use the output register on the BRAM.  Run a simulation to determine the address to data latency.  Use that to tell you when to write the data to the array.

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dpaul24
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Registered: ‎08-07-2014

@katrenoopur ,

The GUI use details are given above.

its shows 1 clock cycle read latency means the data is not exact, after adding output register to the BRAM it shows 2 clocks cycle latency.

if you do not need any extra latency then you remove the option of having the 'output register'. But you have to live with the default 1 cycle latency if you want to use the BRAMs. Why don't you pipeline your design such that your design can read the valid BRAM data after 1 extra clock cycle?

Is there any way to provide the delay in the logic itself?

Delaying the logic means inserting pipeline stages. Insert additional flops....

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katrenoopur
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Registered: ‎12-02-2020

In my case, there is one clock cycle latency and I am not using any output register, now I want to delay the logic by one clock cycle so that I can get the correct data to write into the array.

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katrenoopur
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Registered: ‎12-02-2020

I am not using the output register. I have to manage one clock cycle delay. Should I update the addr of BRAM just after the process start (at rising edge).

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katrenoopur
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Registered: ‎12-02-2020

Yes, I already remove the option of "output register" . Sorry but am not able to understand how can I insert pipeline stages, I tried one more if-else stage to check the address , but it couldn't resolve my issue, Can you show some example code lines. Below is my main logic. I am writing in transposed form.

dat_process: process(clk)
begin
if rising_edge(clk) then



if j = 10 then
addr<= "0000";


else

M(to_integer(unsigned(addr_array)),j) <= test(i);
i <= i + 1;
addr_array <= std_logic_vector(unsigned(addr_array) + 1);


if addr_array = "111" then
j <= j + 1;
i <= 0;
addr <= std_logic_vector(unsigned(addr) + 1);
addr_array <= "000";
end if;


end if;

end if;

end process dat_process;
end Behavioral;

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drjohnsmith
Teacher
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Registered: ‎07-09-2009

Are you used to writing C code ?

VHDL is a hardware description language, 

    what hardware are you describing there ?

 

 

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