How to do a behavior simulation of PLL generated from clocking wizard?

[Leaner]

Hi, I'm a new one using Vivado, and  recently, I'm trying to learn how to achieve behaviour simulation of PLL generated from clocking wizard(20MHz to 240MHz). But I encountered some questions, I need your help.

The source document is shown as below:

module NOT_gate(
input in,
//input reset,
output out
    );
//    assign out = ~in;
clk_wiz_0 pll(.clk_out1(out), .clk_in1(in));
endmodule

The testbench:

module simulation(

    );
    reg clk = 0;
    always #50 clk = ~clk;
    
    wire out;
//    wire reset = 0;
    NOT_gate NOT(.in(clk), .out(out));
endmodule

And the simulation results:

Thanks for helping me.

[lettertu · Accepted solution]

Hi @Leaner ,

To generate a 20MHz clock stimulus, it should be:

always #25 clk = ~clk;

And before the your module "simulation" definition, you have to specify the timescale:

`timescale 1ns / 1ps

Then, run the simulation longer than 20us to wait for the generated clock being locked.

[Leaner]

Thanks for your reply, and now, I can get right results!

But, I have a new questions about the results, the simulation result is as follows:

 The output of PLL is ok after about 3.3us. How to understand the results between 0 ~ 3us?

Thanks for helping me.

[lettertu]

Hi @Leaner 

That's how the MMCM/PLL works. It must cost some time to achieved phase alignment within a predefined window and frequency matching within a predefined PPM range.

LOCKED will be asserted after the output clock gets stable if it's enabled in the IP.

[Leaner]

Thank you very much, I get it.

Do you know which user guide documents cover the principle of PLL(including explanation of the reset, locked, etc)?

Thanks for your reply.

[lettertu]

Hi @Leaner 

UG472 for 7-ser devices, UG572 for US/US+ devices.

PG065 for the Clocking Wizard IP.

[Leaner]

Thanks!

[dhanushx012]

Didnt expect to get a direct answer so soon! Thank you!

[Leaner]

Do you meet the same problem?