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Visitor
Visitor
1,689 Views
Registered: ‎08-27-2018

How to implement large bit width and small depth single port or dual port sram on ultra scale FPGA: such as 16*1024 (depth:16, width: 1024 bits)?

I our project, we need a lot of large bit width and small depth high speed sram on ultra scale FPGA (VU9P), the size of required sram is 16*1024 (depth: 16 entry, width: 1024 bit). But both block ram and ultra ram have large depth, small width, num of them can compose one required sram, but it is a waste of the FPGA storage resource and chip area. Is there any good solution for this issue?

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Moderator
Moderator
1,669 Views
Registered: ‎08-08-2017

Hi @robin_zheng

 

The memory size configuration (Write_width = 1024 and Depth =16) is supported.

 

Capture.PNG

 

 

The Small data width limitation is for URAM (72 bits wide with lower 64 bits used for data and upper 8 bits used for paity or for the regular data inputs)

 

 

Can you please elaborate your requirement further?

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Contributor
Contributor
1,633 Views
Registered: ‎09-14-2017

That implementation wastes huge amount of memory, it needs 15 BRAMs (522kbit) to implement 16kbit memory due to BRAM data port sizes. It might make sense to implement this from LUTRAM if you have a lot of LUTs free (routing congestion though might become a problem). Or if your clock frequency is low enough you could run the memory at double speed and write two words to memory to halve the amount of BRAMs. 

 

--Kim

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Visitor
Visitor
1,629 Views
Registered: ‎08-27-2018

Thanks! We will try to balance resource with other modules, and try to use LUT ram to build my buffers.

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