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adam_mira
Participant
Participant
464 Views
Registered: ‎01-13-2020

How to link jesd204 PHY to a specific clock?

Hi,

In short:

How can I connect two jesd204 PHYs to the same QPLL output?

 

More information:

My goal is to instantiate two jesd204 PHYs using two GTH3 channels in the -same- quad.

The ref clock to both of the PHYs goes through QPLL0, so the ref clock port called "QPLL0_REFCLK".

With one PHY there is no problem. I'm connecting MGT_CLK to the port and its work as expected.

With two PHYs I'm connecting MGT_CLK to both ports but the "Place design" stage fail.

My question: 

How can I connect two jesd204 PHYs to the same QPLL output?

Thank you,

Adam.

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2 Replies
roym
Moderator
Moderator
423 Views
Registered: ‎07-30-2007

When you put 2 designs into the same quad both designs will instantiate a GT_COMMON for the QPLL and an input buffer for the refclk.  Since they are sharing these resources you must remove and input refclk buffer and the GT_COMMON from one design and wire the refclk buffer output and GT_COMMON outputs from the other design to drive the orphaned lines in the first design.  You will need to get the input buffer and the GT_COMMON into the example design to accomplish this.  I'm not sure how easy this is with the JESD IP.




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rkhatri
Moderator
Moderator
359 Views
Registered: ‎01-10-2019

Hi @adam_mira ,

There is an AR which may be helpful.

https://www.xilinx.com/support/answers/65228.html

 

Thanks,
Rahul Khatri
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