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1,055 Views
Registered: ‎04-16-2017

How to read whole data of True Dual Port BRAM?

Hi folks,

 

I'm trying to instantiate TDP BRAM using Block Memory Generator of size 1024. I set Write Width=32 and Read Depth=32 for port A, so the size is 32x32 = 1024. Now, I want to have Read Width=1024 for port B so that I can read all 1024 bits as one location. The minimum allowable Read Depth for port B, in this case, is 2 (what the tool shows). My question is, is there any way to instantiate or infer this size of BRAM with these properties? as I also tried using RTL and it gives me an error 'Port Aspect Ratio is mismatched with the Read Depth Ratio.

 

I know there is a relationship between Port Aspect Ratio and Read Depth Ratio. But in my case, it shouldn't be any mismatch as my Port Aspect Ratio (for Reading Widths of ports A & B) is 32:1024 i.e. 1:32 while the Read Depth ratio is also 1:32.

Even when I'm inferring BRAM using RTL the tools sets the Read Depth ratio as 1:16 by itself and shows me that there is a mismatch.

 

Any Solutions? or it is an architectural issue? Why don't we read whole data at the same time as one location?

 

Thanks!

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4 Replies
Moderator
Moderator
1,029 Views
Registered: ‎08-08-2017

Re: How to read whole data of True Dual Port BRAM?

Hi uzaifsharif@yahoo.com

 

The block memory generator core supports port aspect ratios of 1:32. i.e The port A data width can be up to 32 times larger than the port B data width, or vice versa. 

 

I have checked this at my end and BMG is not supporting selection of 1024 as read Width. 

BRAM.PNG

 

 I will check it internally and get back to you.

 

Have you tried this configuration using Macro ( XPM_MEMORY_TDPRAM) ?

Please find the Instantiation of this in the user guide

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug974-vivado-ultrascale-libraries.pdf  -> page131.

 

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1,018 Views
Registered: ‎04-16-2017

Re: How to read whole data of True Dual Port BRAM?

Hi Pthakare,

 

First of all thank you so much for your reply. I also raised the same issue directly to one of the Xilinx's guys.

I tried using RAMB36E1 and RAMB36E2 primitives, it instantiated a single BRAM but I did have simulation problem in that case. But if I'm gonna go for primitive instantiation then I need to cascade them manually and this will use lots of LUTs to cascade them which isn't a good thing to have.
I didn't try XPM_MEMORY_TDPRAM yet so let me try that I'll let you know if that works!

 

But again we should have that option in BRAM generator logically but I don't know why it doesn't allow that.

 

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Moderator
Moderator
990 Views
Registered: ‎08-08-2017

Re: How to read whole data of True Dual Port BRAM?

Hi uzaifsharif@yahoo.com

 

I checked it internally , The maximum Aspect ratio for TDP is 1:16 only.  This is a primitive restriction .

The Vivado IP Catalog GUI ensures only valid aspect ratios are selected and If we manually instantiate same behavior can be

observed.

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982 Views
Registered: ‎04-16-2017

Re: How to read whole data of True Dual Port BRAM?

Hi Pthakare,

 

The Port Aspect Ratio is basically related with Read Depth Ratio and they have to be same in order to instantiate Block RAM. Please check out the picture below which explains how are they related.

 

1.png

 

So, the conclusion the allowable Read Depth, in any case, is always 2.

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