UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
3,168 Views
Registered: ‎10-17-2016

How to set CONFIG.MEM_WIDTH from the IP tcl script?

Jump to solution

I have created an IP that requires a BRAM block for storage. That same BRAM needs to be accessed via AXI, so I make it a dual port BRAM and connect it to a AXI BRAM Controller. The AXI BRAM Controller sets the BRAM block to 64 bit MEM_WIDTH which is fine.

 

My IP block has a 64 bit wide BRAM_DIN and BRAM_DOUT port, so it would actually fit. The problem: its property CONFIG.MEM_WIDTH gets set to 32 bit by default.

 

How can I set this property from the VHDL source or from the tcl script, so it will get set correctly when adding the IP block?

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Adventurer
Adventurer
5,299 Views
Registered: ‎10-17-2016

Re: How to set CONFIG.MEM_WIDTH from the IP tcl script?

Jump to solution

My problem was that the data width was automatically set to 32 bit. I had to set it to 64 bit in VHDL using

 

ATTRIBUTE X_INTERFACE_INFO of bram_rddata: SIGNAL is "xilinx.com:interface:bram:1.0 bram DIN";
ATTRIBUTE X_INTERFACE_PARAMETER of bram_rddata: SIGNAL is "MASTER_TYPE BRAM_CTRL,MEM_ECC NONE,MEM_WIDTH 64,MEM_SIZE 1048576";

Without these lines, the data width would always be set to 32 bit automatically for my block. The AXI BRAM controller connected to the same BRAM block would be set to 64 bit, causing an error message during elaboration: 'non-matching width is not supported by BRAM generator.'

The automatic determination of the data width did not work for me..

Also, after re-packaging my IP with the ATTRIBUTE fix, I had to remove my block from the block design and re-add it. Simply upgrading the IP block did not fix the data width!

View solution in original post

0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
2,960 Views
Registered: ‎08-01-2008

Re: How to set CONFIG.MEM_WIDTH from the IP tcl script?

Jump to solution
In IPI flow, all the parameters are automatically determined and most of them are kept read only. Width size depends upon your AXI master device. Depth you can modify using address editor
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Highlighted
Adventurer
Adventurer
5,300 Views
Registered: ‎10-17-2016

Re: How to set CONFIG.MEM_WIDTH from the IP tcl script?

Jump to solution

My problem was that the data width was automatically set to 32 bit. I had to set it to 64 bit in VHDL using

 

ATTRIBUTE X_INTERFACE_INFO of bram_rddata: SIGNAL is "xilinx.com:interface:bram:1.0 bram DIN";
ATTRIBUTE X_INTERFACE_PARAMETER of bram_rddata: SIGNAL is "MASTER_TYPE BRAM_CTRL,MEM_ECC NONE,MEM_WIDTH 64,MEM_SIZE 1048576";

Without these lines, the data width would always be set to 32 bit automatically for my block. The AXI BRAM controller connected to the same BRAM block would be set to 64 bit, causing an error message during elaboration: 'non-matching width is not supported by BRAM generator.'

The automatic determination of the data width did not work for me..

Also, after re-packaging my IP with the ATTRIBUTE fix, I had to remove my block from the block design and re-add it. Simply upgrading the IP block did not fix the data width!

View solution in original post

0 Kudos