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katrenoopur
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Registered: ‎12-02-2020

How to write in and out from fifo in VHDL using xilinx ISE

I am trying to create FIFO in VHDL, 16 word depth and 4 bit width, I'm not able to write in and out from fifo. Kindly help me in this. It seems like programm is not entering into the process. Signals that I am using is not updating. I am using Xilinx ISE IP Core to instantiate the FIFO . Asynchrous reset with value 0 is used.Here is the code

////

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;


entity fifo_practice is

    generic (
    addr_width : integer := 4;          -- address width
    data_width : integer := 4);         -- data width

   Port 
    (       clk : in  STD_LOGIC;
                rst : in  STD_LOGIC;
                
                din : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                
                full: OUT STD_LOGIC;
                empty: OUT STD_LOGIC;
                
                test: OUT STD_LOGIC;
                
                dout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
                );
end fifo_practice;

architecture Behavioral of fifo_practice is


COMPONENT fifo1_module1
  PORT (
    clk : IN STD_LOGIC;
    rst : IN STD_LOGIC;
    
     din : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    
     wr_en : IN STD_LOGIC;
    rd_en : IN STD_LOGIC;
    
     dout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    
     full : OUT STD_LOGIC;
    empty : OUT STD_LOGIC
  );
END COMPONENT;

--signal full : STD_LOGIC  := '0';
--signal empty : STD_LOGIC := '0';
signal wr_en : STD_LOGIC := '0';
signal rd_en : STD_LOGIC := '0';

constant depth : integer := 2**addr_width;
signal readptr,writeptr : std_logic_vector( addr_width-1 downto 0); --read and write pointers.
signal full0 : std_logic;
signal empty0 : std_logic;

begin
    
    --full <= full0;
    --empty <= empty0;

module1_fifo1 : fifo1_module1
  
  PORT MAP (
    clk => clk,
    rst => rst,
    din => din,
    wr_en => wr_en,
    rd_en => rd_en,
    dout => dout,
    full => full0,
    empty => empty0
  );
    
    

fifo0: process(clk,rst)

    begin

        if rst = '0' then

            readptr <= (others => '0');
            writeptr <= (others => '0');
            empty0 <= '1';
            full0 <= '0';



        else
            if rising_edge(clk) then

                if (writeptr + '1' = depth-1) then
                    full0<='1';
                else
                    full0<='0';
                end if ;
                
                    
                if (readptr = writeptr ) then
                    empty0<='1';
                else
                    empty0<='0';
                end if ;    



                if wr_en='1' and full0='0' then
                
                    writeptr <= writeptr + '1' ;
                end if ;

                if rd_en='1' and empty0='0' then
                    
                    readptr <= readptr + '1' ;
                end if ;

                
            end if;
        end if;
    end process;
end Behavioral;




 

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