01-14-2020 03:53 AM
（if you use AD9689 and jesd204b core, could you contact me via e-mail email@example.com）
I am using jesd204b ip core and the lane link rate is 12.5Gb/s. The refclk of jesd204b is 312.5MHz which is product by HMC7044 and jesd204b core works but when I use the clock signal which is product by jesd204b (I call it ‘user_clk’) core to drive an ILA, of which the probes are jesd204b core lane data. But when I program bits file, ILA always note the ILA core clock has stopped.
Figure 1 jesd204b ip core configuration, Figure 2 XCKU040 FPGA JESD204B clock (GT_POWERGOOD signal may cause the ‘user_clk’ not free-running clock?)
Figure 3 result error
01-14-2020 04:25 AM
Hi firstname.lastname@example.org ,
when you are specifying which signals are going to be captured, you should also specify to which clock they are connected. Is the selected clock stable?
I would recommend to use some stable clock on which runs most of the design and check status of the QPLL as well as status of other clock signals.
01-14-2020 06:13 AM
thanks a lot. But In my project, there only two clock 125MHz from PC which is used for drive spi module,etc and 312.5MHz from HMC7044 which is used for jesd204b. And if i am specifying which signals are going to be captured (jesd204b output data)are only synchronous with user_clk(jesd204b core output 312.5MHz), and i don't have other clock to drive ILA, how to do?
And how can I check a clock is stable?
and how can I check QPLL's status?
to be honest, I also think the clock which drive ILA is not stable but it exists actually.
01-14-2020 12:08 PM
Hi email@example.com ,
when I bring up the board, the first think to check are clocks. Actually, in several products I worked on, we had one diode connected to system clock so it blinked with predefined frequency to be sure that at least clocks works.
You do not write if the board you are working on is new design or if it is already tested development board. If it is tested, you should know, which clocks are reliable. I believe, that HMC7044 can be reprogrammed through SPI so is this setting correct? If your board is new, you will have to check at least one clocks with osciloscope.
I check stability of the clocks by two simple counters (plus some logic around). Basically, I take some known interval (10ms?) measured by the stable clock(first counter). At the beginnign of the interval I reset second counter. Than the second couter is counting +1 for every clock cycle of measured clock and at the end of interval I see the speed of the clock. The I check if this value is stable(+- few clock cycles) for some predefined time (100 iteration?). This did help me few times when the clock were issue (incorrectly set PLL, incorrect crystall, connection issues.)
By the QPLL status I meant signals such as QPLL1LOCK or QPLL0LOCKEN etc. To see if the QPLL is locked, enabled, etc.
I hope this will be helpfull