cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jorgitog1
Contributor
Contributor
861 Views
Registered: ‎06-17-2015

IP Packager not reflecting block diagram ports

Jump to solution

Here is my block diagram (Vivado 2018.1):

IP_Block_Diagram.PNG

When I click on the Package IP link on the Flow Navigator section and select Ports and Interfaces the Phase_Inc[31:0] is not included in the list of Ports and Interfaces:

PortsAndInterfaces.PNG

If somebody could tell me what am I doing wrong I would greatly appreciate it.

Thanks for all your help.

 

0 Kudos
1 Solution

Accepted Solutions
ashishd
Xilinx Employee
Xilinx Employee
696 Views
Registered: ‎02-14-2014

Hello @jorgitog1 ,

When I tried to add module Serializer to block design, I received below critical warning -

CRITICAL WARNING: [IP_Flow 19-4751] Bus Interface 'chip_clock': FREQ_HZ bus parameter is missing for output clock interface.

For successful inference of clocks, resets, interrupts and clock enables, it is required that proper attributes are in place in the top level HDL code. So after I added FREQ_HZ parameter for chip_clock signal (I assumed it to be 200 MHz but when I looked at your module, it is slower clock derived from 400 MHz clock), I could get past this critical warning and correctly package this block design as custom IP. I have attached modified RTL for your reference. 

You need to correctly calculate frequency of chip_clock signal and replace 200 MHz with that calculated value. 

After this if you still encounter any problem, please share output script generated after using command - write_bd_tcl recreate.tcl 

Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

5 Replies
ashishd
Xilinx Employee
Xilinx Employee
850 Views
Registered: ‎02-14-2014

Hello @jorgitog1 ,

As it can be seen in the second snapshot which you've posted, there is 1 warning at 'Ports and Interfaces' tab. I think it should convey information about why Phase_Inc[31:0] is not included in list of ports.

Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
jorgitog1
Contributor
Contributor
839 Views
Registered: ‎06-17-2015

I added an HDL wrapper to the Block Diagram and was able to see the Phase_Inc port on the Ports and Interfaces section.PortsAndInterfaces.PNG

Unfortunately, I am now getting the following error:

Error.PNG

This chip_clock signal is the output of an internal block (Serializer_v1_0) and as you can see in the original block diagram, it is not connected t a port.

Does anybody know the reason for this error?

0 Kudos
ashishd
Xilinx Employee
Xilinx Employee
811 Views
Registered: ‎02-14-2014

Hello @jorgitog1 ,

Can you attach RTL file for serializer_0 module ?

Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
jorgitog1
Contributor
Contributor
802 Views
Registered: ‎06-17-2015

 

 

 

 

Here is the RTL for the Serializer module:


module Serializer(
input clk_400Mhz, // Input clock - Assuming 400 Mhz
input areset, // This is an active low reset signal
input Load, // The rising edge of this signal will load the 32 bits present in the Pin input
input [31:0] Pin, // This 32 bits will be coming from the FIFO output
output Done, // The rising edge of this signal will indicate completion of transmission for all the bits within the pulse
output Sout, // This is the serialized output of Pin
output FifoEn, // This is an active high signal used to set the write enable input of the FIFO
output RdClk, // This is the read clock of the FIFO
output chip_clock // This is the chip clock output to be used to shift out Sout
);
reg [31:0] rPin;
reg [31:0] rPinTmp;
reg rSout, Shifting, rLoad0, rLoad1, rDone, rchip_clock, rRdClk, rRdClk0, rRdClk1, rFifoEn;
integer iShiftCount, iClockCount, iChipCount, iTotalBitCount;


// Total Bit Count
always @(negedge areset,posedge rchip_clock)
begin
if (areset == 1'b0) begin
rDone = 1'b1;
iTotalBitCount = 0;
end
else if (rchip_clock == 1'b1) begin
if(Shifting == 1'b1) begin
if(iTotalBitCount < 25000) begin
rDone = 1'b0;
iTotalBitCount = iTotalBitCount + 1;
end
else begin
iTotalBitCount = 0;
rDone = 1'b1;
end
end
end
end

// Generate Slower Clock
always @(negedge areset,posedge clk_400Mhz)
begin
if (areset == 1'b0) begin
rchip_clock = 1'b0;
iClockCount = 0;
end
else if (clk_400Mhz == 1'b1) begin
if(Shifting == 1'b1) begin
if (iClockCount <49) begin
iClockCount = iClockCount + 1;
end
else begin
iClockCount = 0;
rchip_clock = !rchip_clock;
end
end
end
end

// Serialize
always @(negedge areset, posedge rchip_clock, posedge Load, posedge rRdClk, negedge rchip_clock)
begin
if (areset == 1'b0) begin
rPin = 32'h00000000;
rSout = 1'b0;
iShiftCount = 0;
rRdClk = 1'b0;
rPinTmp = 32'h00000000;
Shifting = 1'b0;
end
else if ((rRdClk == 1'b1)/* &&(rchip_clock == 1'b0)*/)begin
rRdClk = 1'b0;
iShiftCount = 0;
rSout = rPinTmp[0:0];
rPinTmp = rPinTmp >> 1;
iShiftCount = iShiftCount + 1;
end
else if (((Load == 1'b1)&&(rDone == 1'b1)/*||(rRdClk == 1'b1)*/)/*&&(Shifting == 1'b0)*/) begin
Shifting = 1'b1;
rPinTmp = Pin;
iShiftCount = 0;
end
else if((Shifting == 1'b1) && (iShiftCount >31) &&(rRdClk == 1'b0))begin
rRdClk = 1'b1;
rPinTmp = Pin;

end
else if (rchip_clock == 1'b1) begin
if((Shifting == 1'b1) && (iShiftCount <=32)) begin
rSout = rPinTmp[0:0];
rPinTmp = rPinTmp >> 1;
iShiftCount = iShiftCount + 1;
rRdClk = 1'b0;
end
else begin
iShiftCount = 1;
end
end
end

// Register Values
always @(negedge areset, posedge clk_400Mhz)
begin
if (areset == 1'b0) begin
rLoad0 = 1'b0;
rLoad1 = 1'b0;
rFifoEn = 1'b0;
rRdClk1 = 1'b0;
rRdClk0 = 1'b0;
end
else if (clk_400Mhz == 1'b1) begin
rLoad1 = rLoad0;
rLoad0 = Load;// | rRdClk0;
rRdClk1 = rRdClk0;
rRdClk0 = rRdClk;
if((rLoad1 == 1'b0) && (rLoad0 == 1'b1)) begin
rFifoEn = 1'b1;
end
end
end
assign Sout = rSout;
assign Done = rDone;
assign chip_clock = rchip_clock;
assign RdClk = rRdClk0;
assign FifoEn = rFifoEn;

endmodule

0 Kudos
ashishd
Xilinx Employee
Xilinx Employee
697 Views
Registered: ‎02-14-2014

Hello @jorgitog1 ,

When I tried to add module Serializer to block design, I received below critical warning -

CRITICAL WARNING: [IP_Flow 19-4751] Bus Interface 'chip_clock': FREQ_HZ bus parameter is missing for output clock interface.

For successful inference of clocks, resets, interrupts and clock enables, it is required that proper attributes are in place in the top level HDL code. So after I added FREQ_HZ parameter for chip_clock signal (I assumed it to be 200 MHz but when I looked at your module, it is slower clock derived from 400 MHz clock), I could get past this critical warning and correctly package this block design as custom IP. I have attached modified RTL for your reference. 

You need to correctly calculate frequency of chip_clock signal and replace 200 MHz with that calculated value. 

After this if you still encounter any problem, please share output script generated after using command - write_bd_tcl recreate.tcl 

Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post