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5,272 Views
Registered: ‎01-22-2015

IP for UltraRAM

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The image below is from Xilinx document, pg058 (page 95), showing that the Block Memory Generator v8.4 (BMG84) can be used to configure UltraRAM (URAM) for UltraScale+ FPGAs.

BMG84_pg058.jpg

 

However, BMG84 in WebPack Vivado v2017.4 (for Kintex UltraScale+ project) is shown by the following image.

BMG84_2017p4.jpg

 

Should I be able to configure URAM using BMG84 in WebPack Vivado v2017.4?

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Observer clarkchris
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Registered: ‎07-20-2017

Re: IP for UltraRAM

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In 2018.2, when running Block Memory Generator 8.4 from IP Catalog, there is no option to select URAM.

 

However, when running Block Memory Generator 8.4 from an IP Integrator Block Design, it is possible to choose primitive type of BRAM or URAM.

 

Outside of a block design, URAM memories and FIFOs can be instantiated using XPM libraries.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: IP for UltraRAM

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yes you can configure block Memory Generator for URAM IP . you may also use XPM_Memory from language template
Thanks and Regards
Balkrishan
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5,223 Views
Registered: ‎01-22-2015

Re: IP for UltraRAM

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Hi Balkrishan,

 

Thanks for your reply!

 

The problem is that the image of Block Memory Generator from Xilinx document, pg058, shows three checkboxes called "BRAM", "URAM", and "AUTO".  So, you can use these checkboxes to indicate that you want URAM.  Howevever, in Vivado Webpack v2017.4, the Block Memory Generator does not have these checkboxes. 

 

Do I need to wait for the next release of Vivado to see the "BRAM", "URAM", and "AUTO" checkboxes in Block Memory Generator?

 

Thanks,

Mark

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: IP for UltraRAM

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please make sure you are using supported device . In case still seeing issue please share XCI file

Thanks and Regards
Balkrishan
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5,205 Views
Registered: ‎01-22-2015

Re: IP for UltraRAM

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Hi Balkrishan,

 

Again, thank you for answering my post.

 

I am using device XCKU5P (specifically xcku5p-ffva676-3-e), which I see from the Xilinx website is supported by Webpack Vivado v2017.4.

 

Attached is XCI file created by Block Memory Generator v8.4.  I was trying to create URAM of size 4096x72 but ended up creating Block-RAM (BRAM) because the Block Memory Generator v8.4 gave me no options for selecting URAM.

 

Mark

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5,187 Views
Registered: ‎01-22-2015

Re: IP for UltraRAM

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Hi Balkrishan,

 

I fear that my question is not clear.

 

The problem is that the following three checkboxes do not appear in Block Memory Generator v8.4 (BMG84)  of Vivado v2017.4. 

 

Primitive_Type.jpg

Maybe I need to wait for next version of Vivado to see these checkboxes?

 

Thanks,

Mark

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Observer dasidler
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Registered: ‎04-23-2014

Re: IP for UltraRAM

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markg@prosensing.com I just run into the same issue. Did you in the meantime find a way how to use URAM in the Block Memory Generator?

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4,773 Views
Registered: ‎01-22-2015

Re: IP for UltraRAM

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I have not yet been able to instantiate (ie. use IP) for URAM.  -although, I've not yet tried the latest version of Vivado.

 

I am able to infer URAM using HDL code that comes with ug901.  In the post <here> you will find more description of inferring URAM and some problems I encountered.

 

Mark

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Observer dasidler
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Registered: ‎04-23-2014

Re: IP for UltraRAM

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Thanks for the feedback.
I tried it in version 2018.1, the Block Memory Generator is still at version 8.4 and there is no option to choose URAM.

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Observer clarkchris
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Registered: ‎07-20-2017

Re: IP for UltraRAM

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In 2018.2, when running Block Memory Generator 8.4 from IP Catalog, there is no option to select URAM.

 

However, when running Block Memory Generator 8.4 from an IP Integrator Block Design, it is possible to choose primitive type of BRAM or URAM.

 

Outside of a block design, URAM memories and FIFOs can be instantiated using XPM libraries.

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Moderator
Moderator
3,570 Views
Registered: ‎08-08-2017

Re: IP for UltraRAM

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markg@prosensing.com

 

Yes, As mentioned by @clarkchris URAM selection is only supported through IPI flow.

 

We are encouraging customer to use the XPM base implementation and URAM can be infer through XMP by setting Memory_Primitive = "Ultra"

 

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3,556 Views
Registered: ‎01-22-2015

Re: IP for UltraRAM

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@clarkchris and @pthakare

Thank you for answering my very old question!

 

@pthakare

     We are encouraging customer to use the XPM base implementation...

This sounds like a big change to things!   Are you saying that for all IP we will be seeing less of the friendly setup wizards  - and more of the manual setup procedure used by XPM?

 

Thanks,

Mark

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Visitor timosau
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Registered: ‎10-07-2014

Re: IP for UltraRAM

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Hello all,

I have to comment this thread as I run in same issue with my design. But little bit different angle.

I try to make everything in IPI if possible.

I have used to use AXI bram controller and BMG as pair and was glad to find out that BMG has URAM option.

That actually worked ok, exept that clock rate of memory was poor. Reason is that no register are used.

I found out that there is parameter "Register_PortA_Output_of_Memory_core" and "Register_PortA_Output_of_Memory_Primitive" and if I set them to "true" performance if naturally better.

But AXI BRAM controller can't handle added read latency!

And as mentioned by Mark, I can't generate IP with AXI interface and URAM primitive.

 

So now I wonder, should I hack AXI BRAM controller or hack generated BMG IP or wait Xilinx support for registered URAM in IPI. 

I'm confused why there is so big difference in IPI IP and standalone IP. I quest that something to do with IPI automation but why standalone version lacks URAM is strange.

 

Timo


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Moderator
Moderator
3,216 Views
Registered: ‎08-08-2017

Re: IP for UltraRAM

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Hi @timosau

We consider this requirement and added the read latency support for URAM when selected through IP integrator in VIVADO 2018.3 (tentative release schedule is 

mid of this month)

This is the note from BMG  change log.

uram.png

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Visitor timosau
Visitor
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Registered: ‎10-07-2014

Re: IP for UltraRAM

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Thank you for quick and incisive answer.

Lets hope that BRAM controller also get required update and update is in schedule:)

T:Timo

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