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Observer
Observer
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Registered: ‎06-14-2018

ISERDESE2 unexpected output

Hi,

I'm using the ISERDES2 with the below configuration and see that only the Q1 and Q2 are outputing a data.

Please let me know what am I doing wrong in the simulation?

Some more info:

CLK -> 50Mhz

CLK_DIV -> 12.5Mhz

 

Thx

Neta

// declare the iserdes
ISERDESE2
# (
.DATA_RATE ("DDR"),
.DATA_WIDTH (8),
.INTERFACE_TYPE ("NETWORKING"),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.NUM_CE (2),
.OFB_USED ("FALSE"),
.IOBDELAY ("NONE"), // Use input at D to output the data on Q
.SERDES_MODE ("MASTER"))
iserdese2_master (
.Q1 (iserdes_q[0][pin_count]),
.Q2 (iserdes_q[1][pin_count]),
.Q3 (iserdes_q[2][pin_count]),
.Q4 (iserdes_q[3][pin_count]),
.Q5 (iserdes_q[4][pin_count]),
.Q6 (iserdes_q[5][pin_count]),
.Q7 (iserdes_q[6][pin_count]),
.Q8 (iserdes_q[7][pin_count]),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (bitslip[pin_count]), // 1-bit Invoke Bitslip. This can be used with any DATA_WIDTH, cascaded or not.
// The amount of BITSLIP is fixed by the DATA_WIDTH selection.
.CE1 (clock_enable), // 1-bit Clock enable input
.CE2 (clock_enable), // 1-bit Clock enable input
.CLK (clk_in_int_buf), // Fast source synchronous clock driven by BUFIO
.CLKB (clk_in_int_inv), // Locally inverted fast
.CLKDIV (clk_div), // Slow clock from BUFR.
.CLKDIVP (1'b0),
.D (data_in_from_pins_delay[pin_count]), // 1-bit Input signal from IOB
.DDLY (1'b0), // 1-bit Input from Input Delay component
.RST (io_reset), // 1-bit Asynchronous reset only.
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
// unused connections
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.OFB (1'b0),
.OCLK (1'b0),
.OCLKB (1'b0),
.O ()); // unregistered output of ISERDES

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