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Contributor
Contributor
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Registered: ‎06-25-2017

Independent Clock FIFO's Post-Synth Timing Simulation,Post-Synth Function Simulation and Behavior Simulation are different

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Dear  forums,   

    I used FIFO Generator of IP Catalog at Vivado 2015.2 to generate a  Independent Clock FIFO in which read data width and write data width are different.However, Post-Synth Timing Simulation,Post-Synth Function Simulation and Behavior Simulation are different.But Behavior Simulation is exactly what I want.Please see it as below.

 

Behavioral Simulation1.JPG

din is the input of write data for FIFO,and din is a "wire".assgin din = {datain4,datain3,datain2,datain1};

 

Behavioral Simulation2.JPG

 

As above,doutdata is the read data of FIFO and doutvalid is the output valid signal.It is exactly correct.

 

Post-Synthesis Simulation—Functional.JPG

 

As above,this is Post_Synth Functional Simulation,The first eight doutdata are correct and last four datadata  are incorrect.

 

Post-Synthesis Simulation—Timing.JPG

 

As above,this is Post-Synth Timing Simulation.The first din which is {16'd207,16'd206,16'd205,16'd205} is not as output.

 

    I am confused where is wrong.

    By the way,Post-Synth Functional Simulation is the same as Post-Implementation Functional Simulation.And Post-Synth Timing Simulation is the same as Post-Implementation Timing Simulation.

 

   Please see the customization of FIFO as below.

FIFO1JPG.JPG 

 

FIFO2.JPG

 

Last,I would like to post my Xilinx files to be modified by you,Thanks.

'buffer1_top.v' is the top file of my module. 

'test.v' is the file for simulation. 

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Moderator
Moderator
4,316 Views
Registered: ‎08-01-2007

Re: Independent Clock FIFO's Post-Synth Timing Simulation,Post-Synth Function Simulation and Behavior Simulation are different

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1. Try to use the latest Vivado version and re-generate the IP.

2. Change the simulator to Vivado Simulator.

3. Delay all the fifo inputs by 1/4 clock cycle to check it.

View solution in original post

1 Reply
Highlighted
Moderator
Moderator
4,317 Views
Registered: ‎08-01-2007

Re: Independent Clock FIFO's Post-Synth Timing Simulation,Post-Synth Function Simulation and Behavior Simulation are different

Jump to solution

1. Try to use the latest Vivado version and re-generate the IP.

2. Change the simulator to Vivado Simulator.

3. Delay all the fifo inputs by 1/4 clock cycle to check it.

View solution in original post