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Adventurer
Adventurer
596 Views
Registered: ‎11-18-2017

Independent clock FIFO remains empty.

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Hello.

I'm using Vivado 2018.2 to create a simple logic with a FIFO.

The FIFO has an write clock of 200 MHz and read clock of 100 MHz.

I wrote a simple code as below.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity independent_clock_fifo is

    Port 
    (
        reset_i     : in std_logic;
        
        data_i      : in std_logic_vector(3 downto 0);
        wr_en_i     : in std_logic;
        clk_wr_i    : in std_logic;
        
        data_o      : out std_logic_vector(3 downto 0);
        rd_en_i     : in std_logic;
        clk_rd_i    : in std_logic;
        
        full_o      : out std_logic;
        empty_o     : out std_logic
     );
     
end independent_clock_fifo;

architecture Behavioral of independent_clock_fifo is

    component fifo_generator_0
        PORT 
        (
            srst        : IN STD_LOGIC;
            
            din         : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            wr_en       : IN STD_LOGIC;
            wr_clk      : IN STD_LOGIC;
            
            dout        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
            rd_en       : IN STD_LOGIC;
            rd_clk      : IN STD_LOGIC;
                       
            full        : OUT STD_LOGIC;
            empty       : OUT STD_LOGIC;
            wr_rst_busy : OUT STD_LOGIC;
            rd_rst_busy : OUT STD_LOGIC
        );
    end component;
    
begin

    inst_fifo_0 : fifo_generator_0
        port map
        (
            srst            => reset_i,
            
            din             => data_i,
            wr_en           => wr_en_i,
            wr_clk          => clk_wr_i,
            
            dout            => data_o,
            rd_en           => rd_en_i,
            rd_clk          => clk_rd_i,
            
            full            => full_o,
            empty           => empty_o,
            wr_rst_busy     => open,
            rd_rst_busy     => open      
        );

end Behavioral;

 

The GUI of IP Catalog for generating a FIFO is like below.

 ff2.JPG

 

ff3.JPG

 

ff4.JPG

 

I created a test bench as below

 

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity independent_clock_fifo_tb is
end;

architecture bench of independent_clock_fifo_tb is

    component independent_clock_fifo
        Port 
        (
            reset_i     : in std_logic;
            
            data_i      : in std_logic_vector(3 downto 0);
            wr_en_i     : in std_logic;
            clk_wr_i    : in std_logic;
            
            data_o      : out std_logic_vector(3 downto 0);
            rd_en_i     : in std_logic;
            clk_rd_i    : in std_logic;
            
            full_o      : out std_logic;
            empty_o     : out std_logic
        );
    end component;
    
    signal reset_i  : std_logic;
    
    signal data_i   : std_logic_vector(3 downto 0);
    signal wr_en_i  : std_logic;
    signal clk_wr_i : std_logic;
    
    signal data_o   : std_logic_vector(3 downto 0);
    signal rd_en_i  : std_logic;
    signal clk_rd_i : std_logic;
    
    signal full_o   : std_logic;
    signal empty_o  : std_logic;
    
    constant clock_period_wr    : time := 5 ns;
    constant clock_period_rd    : time := 10 ns;
    
    signal stop_the_clock       : boolean := false;

begin

    uut: independent_clock_fifo port map 
    ( 
        reset_i     => reset_i,
        data_i      => data_i,
        wr_en_i     => wr_en_i,
        clk_wr_i    => clk_wr_i,
        data_o      => data_o,
        rd_en_i     => rd_en_i,
        clk_rd_i    => clk_rd_i,
        full_o      => full_o,
        empty_o     => empty_o 
    );
    
    stimulus: process
    begin

    reset_i <= '0';
    wr_en_i <= '0';
    rd_en_i <= '0';
    wait for 100 ns;
    
    reset_i <= '1';
    wait for 10 ns;
    
    reset_i <= '0';
    wait for 10 ns;
    
    wr_en_i <= '1';
    data_i <= "1111";
    wait for 5 ns;
    
    data_i <= "1110";
    wait for 5 ns;
    
    data_i <= "1100";
    wait for 5 ns;   
    
    data_i <= "1000";
    wait for 5 ns;   
    
    data_i <= "0000";
    wait for 10 ns;
    
    wr_en_i <= '0';      
    wait;
    end process;
    
    clocking_w: process
    begin
        while not stop_the_clock loop
            clk_wr_i <= '0', '1' after clock_period_wr / 2;
            wait for clock_period_wr;
        end loop;
        wait;
    end process;
    
    clocking_r: process
    begin
        while not stop_the_clock loop
            clk_rd_i <= '0', '1' after clock_period_rd / 2;
            wait for clock_period_rd;
        end loop;
        wait;
    end process;

end;

 

But when I observed the waveform, I found out that the FIFO is not working properly as below figure.

ff5.png

 

Even though I wrote some data through data_i port, the empty_o is still '0'.

Why isn't the FIFO working properly?

 

Thanks for your help.

 

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1 Solution

Accepted Solutions
Highlighted
Adventurer
Adventurer
549 Views
Registered: ‎05-09-2018

Re: Independent clock FIFO remains empty.

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True, however the flag should not require an attempted read. After synchronizing delays the empty flag should update I would take a look inside the FIFO to see what is going on.

View solution in original post

5 Replies
Highlighted
Explorer
Explorer
575 Views
Registered: ‎09-13-2011

Re: Independent clock FIFO remains empty.

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Empty is in the rd_clk domain so I think you need to set the rd_en_i to high to get the correct output.

Highlighted
Scholar
Scholar
565 Views
Registered: ‎08-07-2014

Re: Independent clock FIFO remains empty.

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@kimjaewon,

In order to read data successfully....

fifo_empty must be low. fifo_read must be asserted. I don't see these in your waveform.

On the read side, I only see your read clock toggling.

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Highlighted
Adventurer
Adventurer
550 Views
Registered: ‎05-09-2018

Re: Independent clock FIFO remains empty.

Jump to solution

True, however the flag should not require an attempted read. After synchronizing delays the empty flag should update I would take a look inside the FIFO to see what is going on.

View solution in original post

Highlighted
Teacher
Teacher
539 Views
Registered: ‎07-09-2009

Re: Independent clock FIFO remains empty.

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don't know for definite, but there is I think a statement somewhere about the state of the read / write signals and clock during a reset, how long a reset has to be , and how long after a reset you can access the fifo.

as a qucik go, make the reset happen a good 20 clocks later, and be a good 20 clock of the slowest clock long,

then have a hunt in the fifo docs for the clocks and reset,...

 

one other thing just came to mind, 

     dont wait 10 ns in the test bench,

use the   wait until rising_edge( clk ) 

then you know your delta delasy in the test bench are aligned,

 

 

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Highlighted
Adventurer
Adventurer
523 Views
Registered: ‎11-18-2017

Re: Independent clock FIFO remains empty.

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It seems that I have to wait a long time after reset, then write data into the FIFO.

And empty asserts few moments after I write the data into the FIFO.

Thanks for your help.

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