Inserting the FIFO Gen. AXI register slice to improve interfaces frequency ?
I'd like to know more about the register slice available in the FIFO generator AXI4 stream setting. There is almost nothing written about it in the FIFO generator documents, including its max frequency.
It looks like it can be used to register handshaked interfaces in order to improve frequency and isolate blocks for easier Place and Route. I actually tried to used it this way at a moderate frequency and it worked well, but I wonder if it's really efficient to use it in this purpose.
I would like to use it again to register the user interface of an Aurora IP working @250MHz (the link being @5Gbps) in a Virtex-6 LX75T or 130T. I will have a lot of other pretty fast stuff in my FPGA and therefore, a well optimized logic is necessary. In the Aurora 8b/10b product guide page 31, it is adviced that we keep registered our signals connected to the IP, that is connected to a flip flop. As the register slice is, I believe, more or less a FF, I suppose I can connect the FIFO generator IP set up as register slice directly to the Aurora IP.
1- Is my understanding ok ? Is it recommanded to insert the register slice in order to register handshaked interfaces and improved frequency / place and route ? Or is it better to do it ourself with a normal FF ?
2- What is the typical frequency that should be obtained with the register slice on Virtex-6 and Spartan-6 ? I don't need a precise value, it is just to have an idea.