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vicky28891
Observer
Observer
509 Views
Registered: ‎04-06-2021

Is it possible to read parallely from one BRAM??

Hello everyone,

I am designing one circuit in that I need to have 10 channels of numbers.

The simple way is to use 10 BRAM and read them separately with different read addresses.

But is it possible to implement multiple channels from one BRAM???

 

THanks

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6 Replies
drjohnsmith
Teacher
Teacher
496 Views
Registered: ‎07-09-2009

not all at the same time, 

  but you could put a set of registers on the output of the Bram,

    and control the enable to the one you want to address,

 

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vicky28891
Observer
Observer
481 Views
Registered: ‎04-06-2021

thank you for your reply,

but is there any way that Bram have mulitple read ports rather than one read port.

or this is not supported by ISE or vivado??

 

 

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calibra
Scholar
Scholar
467 Views
Registered: ‎06-20-2012

BRAMs have 2 R/W ports.

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richardhead
Scholar
Scholar
461 Views
Registered: ‎08-01-2012

@vicky28891 

Do they all need to be read independently, or is the same read address applied to all?

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vicky28891
Observer
Observer
436 Views
Registered: ‎04-06-2021

Hi richardhead,

No, all read address will be different.

like for read address for channel1, channel2 ....channel 10  all will be different

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avrumw
Expert
Expert
272 Views
Registered: ‎01-23-2009

but is there any way that Bram have mulitple read ports rather than one read port.

or this is not supported by ISE or vivado??

This has nothing to do with the tools...

The block RAM is a physical cell on the FPGA die. It is a programmable cell that has many different variations that change how it behaves, but one of the defining characteristics of a RAM (as opposed to an array of flip-flops) is that it has a fixed number of access ports - in other words on any one clock it can do only a certain number of operations. In the case of the Xilinx block RAMs, the maximum capability is that it has two read/write ports. These ports can be configured to be read only or write only or both read write; they can be configured to the same width or different width (among a number of defined widths allowed by the cell), they can be run on the same clock or different clocks, they can be 1 clock latency read or two clock latency reads (and a few others), but there are two ports (they are true dual port RAMs).

Avrum