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nishant_gaurav
Visitor
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Registered: ‎08-09-2018

Issue in Generating system management wizard IP

Hello Team,

I am facing an issue in generating system management wizard IP for analog bank 68,69 and 73  of FPGA part (xcvu47p-fsvh2892-3-e)  as the vivado tool is not giving options to select this bank.I have attached the GUI screenshot and  pin details of that part for the reference .I have tried generating with both vivado 2020.1 and vivado 2020.2 version.It is giving option only for 64 to 67, 124 to 127 and 224 to 227.So it is only supporting these banks or i am missing somethings.

please help me in resolving the issue.

 

xadc.jpg

 

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@nishant_gaurav 

The XCVU47P is a 3D IC based on stacked silicon interconnect (SSI) technology.  There are 3 Super Logic Regions (i.e. 3 die) which each have a System Monitor present.

forums_vu47p.png

SLR0 SYSMON is enabled by default.  You need to enable SLR1 SYSMON (Slave0 SYSMON) and/or SLR2 SYSMON (Slave1 SYSMON) to gain access.  This can be enabled on the System Management Wizard Basic tab:

forums_smw_basic.png

forums_smw_extChSel.png

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nishant_gaurav
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Registered: ‎08-09-2018

Hello Mr. Miker,

Thanks for guiding me .

Now i am getting option to generate for 67,68,69,73 bank.But i am facing issue in using this ip in my design.As we require to use 16 channel of bank 67,68,69,73  for monitoring the voltage, i have instantiated 4 sysmon wizard ip - one for bank 67,one for bank 68 and for bank 69 by enabling slave0 sysmon & one for bank73 by enabling slave1 sysmon.But it is throwing error sysmon primitive over utilized as there are only 3 sysmon primitive available and when we are enabling slave sysmon,it consume two sysmon(one for master and one for slave) for single bank.I have generated sysmon wizard ip with interface option None.So,please guide me how i can connect 16 differential channel of bank 67,68,69,73 with xadc or sysmon ip.

error_sysmon.JPG

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nishant_gaurav
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Registered: ‎08-09-2018

Hello Team,

I have one more Query like how many maximum ADC's channels we can use in SYSMON in FPGA part (xcvu47p-fsvh2892-3-e). Please also guide me how can we instantiate sysmon ip in the design for achieving the maximum ADC Channel connection.  

 

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@nishant_gaurav 

While the System Management Wizard provides access to all System Monitors (one in each of SLR), that doesn't mean you can access External Analog Inputs across all SLRs.  Please reference the UltraScale Architecture System Monitor User Guide (UG580; v1.10) in Chapter 1: Overview and Quick Start > SYSMON Pinout RequirementsExternal Analog Inputs section.

forums_ug580_slrs.png

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nishant_gaurav
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Registered: ‎08-09-2018

Hello Mr. Miker,

In the doc it is written we can connect analog input upto 2 banks in one SLR and one bank support upto 16 external analog input.But i am not able to connect sysmon ip to 2 bank also.i have instantiated 2 sysmon wizard ip - one for bank 70  by enabling slave0 sysmone and for bank 73 by enabling slave1 sysmone.But it is throwing error that sysmone4 over utilized .I have generated sysmon wizard ip with interface option None.So,please guide me how i can connect 16 differential channel each of bank 70 and 73 with sysmon IP.Currently i am able to  connect sysmon ip to 16 external differential analog of one bank only.

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@nishant_gaurav 

IO Bank 70 is in SLR 1 and IO Bank 73 is in SLR 2 so you are violating the System Monitor rules.

forums_sysmone4.png

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nishant_gaurav
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Registered: ‎08-09-2018

Thanks Mr. Miker for  quick reply.

So basically i can connect maximum 16 external analog input each for 2 bank in the same SLR like (bank 69,bank 71 or bank 66,bank 67).I have one more doubt like what is the use of 3 sysmon ip present in  FPGA part (xcvu47p-fsvh2892-3-e). Please correct me if i am saying anything wrong.

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@nishant_gaurav 

You can reference the Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency White Paper (WP380; v1.2) which highlights Stacked Silicon Interconnect (SSI) technology.  The VU47P utilizes SSI technology and has 3 individual, identical die on a passive substrate.  Therefore there are 3 SYSMONE4 present unlike only a single SYSMONE4 present in a monolithic die.  Even though there are 3 die, it is treated as a monolithic die/device and provides access to a single SYSMONE4.

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@nishant_gaurav 

Just to clarify the number of external auxiliary analog inputs, you are limited to 16 as that is constrained by the SYSMONE4 architecture.  The SYSMONE4 allows the 16 external auxiliary analog inputs to be spread across 2 IO Banks.

forums_sysmone4_vaux.png

 

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nishant_gaurav
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Registered: ‎08-09-2018

@miker 

Thank you so much for the clarification.

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