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Contributor
Contributor
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Registered: ‎07-24-2009

JESD Phy registers (RXPLL)

Hello!

I'm trying to run JESD at new board and found some incostistency between description of JESD Phy registers and my results. I work with Zynq US+ with Vivado 2019.1. The design uses CPLL for TX and QPLL0 for RX.

Register RXPLL (0xa0) contains value 0x1 which is not correspond to any valid value. PG198 declares Bits 1:0 as:

00 = CPLL
10 = QPLL1 (UltraScale Only)
11 = QPLL (7 series) QPLL0 (UltraScale))

Is there inaccuracy in the description or problem with my design?

 

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