08-21-2020 10:03 AM
I am using JESD Core and JESDPHY core of 4 lanes which has one tx sync input driven from other link partner.
Initially on board reboot, tx_sync input to TX JESD will be high which is as expected.
I observe this strange behavior that, as soon as clock (devclk = 368.64MHz & sysref = 15.36Mhz) is up and asynchronous reset is given to JESD and JESDPHY, on JESD TX link I could see all the 3 phases(CGS,ILAS & Userdata) passing with TX_sync high. But, I am not doing any initialization of other link partner.
As per protocol, CGS phase should only start when other link partner pulls down sync(image is attached), but here it's not. I am giving same 64 bit data to make it 128 bit, So I could see data on lanes 0 and 1 is same as 2 & 3.
I tried giving reset again, with that tx_sync is not triggering low but I could see JESD tx link again passing the phases.
RESET SEQUENCE :
First I am resetting JESD for some long duration of clock cycles, followed by JESD PHY sys_reset and I have followed reset connections properly as per Xilinx answer records,
Also, reset acknowledgement is fine - tx/rx_reset done high continously from PHY core and PLL lock high.
Anybody could tell where has gone wrongwith this JESD behavior..?
08-30-2020 10:28 PM
Hi @raksssss ,
Once in SYNC, there are 3 main reasons a system may fall out of sync / request a resync:
1) CGS is lost on any lane
2) Incorrect transition from 0xBC to the start of ILA is detected
3) Misalignment in received data is detected (alignment codes in data detected at unexpected positions)
- A resync will be triggered when 8 succesive multiframe alignment characters are detected in unexpected places (not at end of multiframe)
If sync is lost shortly after being achieved, could indicate the ADC / DAC settings do not match the JESD204 core settings
1) Settings of ADCs / DACs must match those of the JESD204B core
2) F (octets per frame)
3) K (frame per multiframe)
4) Scrambling / descrambling setting
5) Subclass mode
6) SYSREF handling