cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
raksssss
Adventurer
Adventurer
444 Views
Registered: ‎09-04-2019

JESD receive sync not asserted

Hi,

where could be the issue when JESD receiver at fpga side have lane data other than bcbcbcbc initially to complete CGS phase ? I could see K28.5 char's on lanes but not proper. rxcomma_align signal asserted high,with disparity & notintable errors and sync permanently low. While the TX link is up and stable, RX is not even crossing the CGS phase.

JESD core and phy reset is complete and reset done is high. I am using 4 lanes TX/RX, with LMFS,K = 4421,32, devclk = 368.64MHz, Jesd core clk = line rate/40 , linerate =7.32gbps.

Untitleddd.png

0 Kudos
2 Replies
raj
Adventurer
Adventurer
371 Views
Registered: ‎05-24-2020

@raksssss 

Here is the initialization sequence I am following - 

1) Program clock and wait for its PLL to Lock.

2) Program FPGA

3) Send 1 to rx_reset pin of the JESD RX module.

4) Send 0 to rx_reset pin of JESD RX module.

5) Write 0x2 to JESD RX AXI register 0x04 (fixed reset) to hold the JESD core in reset.

6) Program ADC registers.

7) Clear JESD core reset. After clearing reset, the GT lanes start seeing 0xBCBC characters.

Trigger Sysref

0 Kudos
rkhatri
Moderator
Moderator
332 Views
Registered: ‎01-10-2019

Hi @raksssss,

Have you tried running  the IBERT design first to make sure GT is working fine .

Thanks,
Rahul Khatri
---------------------------------------------------------------------------------
Please Kudo or Accept as a solution, If this Post helped you.
---------------------------------------------------------------------------------
0 Kudos