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Visitor
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Registered: ‎06-08-2018

JESD204 IP CORE Sends rx_sync signal even without error

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I am using JESD RX IP core to read an ADC data. Sometimes the IP core sends rx_sync request to ADC even if there is no error indicated. See screenshot below, rx_frame_error, rxdisperr, and rxnotintable bits are all 0, but rx_sync is still asserted low. Are there any other reasons that could cause the resync happens? How could I reduce the resync events? The data continuity is critical to my project. If one data sample is invalid, the whole data frame has to be discarded. Thank you. 

wendylin_0-1597160052585.png

 

 

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Observer
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Registered: ‎05-24-2020

@wendylin 

Set the trigger position close to the end of the window. Eg - if your window data depth is 8192, set the trigger position to 7000. This way you can see what is happening before rx_sync goes low.

https://www.xilinx.com/support/answers/66921.html

Is the clock and power stable ? Bad signal integrity can also cause the link to go down. You may want to run IBERT on the receiver lanes.

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Observer
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Registered: ‎05-24-2020

@wendylin 

Set the trigger position close to the end of the window. Eg - if your window data depth is 8192, set the trigger position to 7000. This way you can see what is happening before rx_sync goes low.

https://www.xilinx.com/support/answers/66921.html

Is the clock and power stable ? Bad signal integrity can also cause the link to go down. You may want to run IBERT on the receiver lanes.

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Moderator
Moderator
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Registered: ‎01-10-2019

hi @wendylin ,

Once in SYNC, there are 3 main reasons a system may fall out of sync / request a resync:
1) CGS is lost on any lane
2) Incorrect transition from 0xBC to the start of ILA is detected
3) Misalignment in received data is detected (alignment codes in data detected at unexpected positions)
- A resync will be triggered when 8 succesive multiframe alignment characters are detected in unexpected places (not at end of multiframe)

If sync is lost shortly after being achieved, could indicate the ADC / DAC settings do not match the JESD204 core settings
1) Settings of ADCs / DACs must match those of the JESD204B core
2) F (octets per frame)
3) K (frame per multiframe)
4) Scrambling / descrambling setting
5) Subclass mode
6) SYSREF handling

Thanks,
Rahul Khatri
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Visitor
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Registered: ‎06-08-2018

Raj,

 

Thanks for your reply. I set the trigger position close to the end of the window and found several unexpected K-character errors before re-sync. I checked the ADC configuration and "disable FACI uses /K28.7/". Now the re-sync only happens in disparity errors and not-in-table errors. It looks that K28.7 character for frame alignment is not supported by Xilinx JESD204B IP core? 

 

Thanks,

WLin

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Observer
Observer
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Registered: ‎05-24-2020

@wendylinYou can possibly look in to turning off frame alignment in the ADC. Here is an example from ADS54J66 datasheet where it shows the register you can set to turn it off. 

 

Texas instruments ADS54J66Texas instruments ADS54J66

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