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Visitor
Visitor
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Registered: ‎07-16-2020

JESD204 IP under Reset

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Hi,

in my design I'm using 2 JESD204B ip core as TX (see figure below).

 
 

Immagine.png

All other input are the in common for both IP.

The only separate signals are:

- s_axi

- s_axis

- tx_sync

 

After configuration of the 2 ip core (A and B) and after writing the Reset (self clearing), the ip B remain in Reset state (bit 0 of 0x004 register at '1'), the ip A go out of reset state and seems to work correctly.

The configuration is executed first for B and then for A.

What could be the reason why ip B remains in reset state?

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Visitor
Visitor
238 Views
Registered: ‎07-16-2020

Hi, 

I solved the problem by using one PHY for each JESD TX

View solution in original post

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Moderator
Moderator
240 Views
Registered: ‎08-01-2007

s_axi is the interface to write/read registers. How do you reset the IP? By writing to register 0x04? Are the s_axi interfaces of two JESD TX IPs driven by the same input?

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Visitor
Visitor
239 Views
Registered: ‎07-16-2020

Hi, 

I solved the problem by using one PHY for each JESD TX

View solution in original post

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