07-16-2020 06:22 AM
in my design I'm using 2 JESD204B ip core as TX (see figure below).
All other input are the in common for both IP.
The only separate signals are:
After configuration of the 2 ip core (A and B) and after writing the Reset (self clearing), the ip B remain in Reset state (bit 0 of 0x004 register at '1'), the ip A go out of reset state and seems to work correctly.
The configuration is executed first for B and then for A.
What could be the reason why ip B remains in reset state?
07-28-2020 02:07 AM
s_axi is the interface to write/read registers. How do you reset the IP? By writing to register 0x04? Are the s_axi interfaces of two JESD TX IPs driven by the same input?