04-01-2021 01:56 AM - edited 04-01-2021 01:59 AM
I am using JESD204B RX core to read a 4-channel ADC, AD9694. While I was testing the inter-channel synchronization of AD9694, I found that sometimes some noise spikes happen to one of the channels without any disparity error, not-in-table error or frame error detected in the communication. The noise spikes are not from the real signal source either. After the noise spikes, the phase of the waveform in that channel is shifted a little bit.
See the screenshot below for the waveform captured in chA and chD, to which I input the same sinusoidal source. In the screen shot, the noise spikes happened to chD, and no communication errors were detected. After the noise spikes, the two channel become misaligned. The misalignment can last long until a re-sync event happens.
I don't know where the noise spikes could come from, and how can the noses change the alignment of channels. How can I get rid of those noise spikes or at least detect them? The misalignment is not acceptable in my data processing. Any advices would be appreciated. Thank you.
04-08-2021 02:50 PM
Hi @wendylin ,
I have a few questions about your issue:
I hope all of this helps.
Xilinx Product Application Engineer
04-13-2021 03:05 AM
Hi @trevorr ,
Thanks for your reply.
The issue is not specific to channel D, but happens randomly to any channels.
Even if I enable only one channel the issue still presents. Please see the screenshot below, where I enabled only channel B in the ADC, and powered down channel A, C and D. I even set the ADC to output a test pattern, a constant number 8191, but the issue is still there.
I didn't set the fast detect upper threshold, i.e. it is default value 0. I checked the FD pin and it is 0 when the noise issue occurs. I thought it might not be an overage issue, because the noise still presents even if the ADC is set to output a test pattern.
I'm not sure what timing you're asking. I'm using LTC6951 to generate reference clock for the FPGA, ADC and sysref. The sampling rate is 500MHz, the refclk to ADC is 1GHz, and clock to JESD core is 250MHz. The line rate for both ADC and JESD core is 10 GHz. LMFS = 2 2 2 1. Frames per multiframe = 32. SYSREF is sampled on negative edge. LMFC buffer settings is 1024. Let me know if you would like to know other settings.