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Contributor
Contributor
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Registered: ‎07-17-2019

JESD204 Reference design configuration

Hello,

We have a reference design about JESD204 IPs from Xilinx for both tx and rx as can be seen from the attachment.

First, there is a JTAG to AXI master IP connected to the rx and tx JESD IPs. Is this IP to configure the Rx and Tx IPs manually or are they just left connected for us to configure from tcl?.

Secondly, Our frame format is 24410 for Rx and 44210 for tx. What parameters are we supposed to enter to the IP for this frame formats from the IP wizard and are we supposed to enter any parameters other than wizard via JTAG to AXI Master IP. We are a little confused about this.

Thank you for your time and efford

JESD204 reference design.png
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Participant
Participant
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Registered: ‎05-24-2020

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