cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Newbie
Newbie
373 Views
Registered: ‎01-16-2020

JESD204B LogiCore unable to make it work ¿Tips?

Hello all,

I'm working with an ADC (ads42jb69) and I want to interface it with a Kintex 7 FPGA. I'm using the JESD204B IP core for that.

I've set up a JESD204B Rx transceiver but I'm unable to communicate with the ADC (it was working during simulation).

I'm now looking at the charisk and rxdata signals and I'm actually receiving stuff, but it seem to be always receiving it (even with the ADC unpluged) am I reading background noise? Also the SYNC signal is never raised, so it seems that this may be a very basic error.

guixe_0-1596647547819.png

I've checked the clocks and they should be correct.

Sorry if this is a very general question, but I'm kind of lost in this one, any help or tips would be apreciated.

Thanks,

GG

0 Kudos
5 Replies
Highlighted
Moderator
Moderator
331 Views
Registered: ‎08-01-2007

How do you build your link, i.e., what's the TX, what's the RX?

Did you follow the clock scheme "Figure 3‐1: Clock Configuration using Separate refclk and Core Clock" provided on PG066 October 4, 2017? 

Looking at the screenshot, it's not clear if the TX(ADC) is sending out 0xBCBC on gtN_rxdata[31:0]?

---------------------------------------------------------------------------------
Please Kudo or Accept as a solution, If this Post helped you.
---------------------------------------------------------------------------------

0 Kudos
Highlighted
Newbie
Newbie
297 Views
Registered: ‎01-16-2020

Hello nathanx,

The clock scheme is similar to the one to Figure 3.1 but you actually made me find something, reviewing all the clocking again I've found that some configuration is wrong in the ADC and the coreclk is not the correct value.

The clocks are calculated as: Reference clk (250MHz), Core clk (62.5 MHz), sysref is 6.25 MHz and the line rate is 2.5Gbps. It seems that my clock chip is not configuring the core clk to 62.5MHz but to 200MHz, looking at the IP core datasheet: "The core clock always runs at the required rate (1/40th of the serial line rate)"

So it seems that I have to manage a way of reducing that clock frequency. I will leave the post open for some days until I confirm that this fix the problem.

Thanks you very much,

GG
0 Kudos
Highlighted
Newbie
Newbie
220 Views
Registered: ‎01-16-2020

I'm still with the same problem, I fixed the clock but when everything is running I've got a very weird behaviour in most lines.

Line 0 receives BCBCBCBC, but Line 1 never does, Line 2 is always at 00000000 and Line 3 always at FFFFFFFF.

 

Captura.PNG
0 Kudos
Highlighted
Moderator
Moderator
154 Views
Registered: ‎08-01-2007

For JESD204B core designs, Code Group Sync is the first stage of link bring-up. This stage begins once K28.5 K-characters(0xBCBC) are seen on any lane in the link.

Once all lanes see K28.5s (BC alignment characters), Debug Status register (an RX register - see (PG066) Table 2-30 for more information) bit 1 goes high and the Lane has Code Group Sync (CGS is complete).

In the below diagrams, the data are not K-characters, as gtN_rxcharisk[3:0] is not high.

0 Kudos
Highlighted
Observer
Observer
131 Views
Registered: ‎05-24-2020

@guixe 

Here is the initialization sequence I am following - 

1) Program LMK and wait for PLL2 Lock.

2) Program FPGA

3) Send 1 to rx_reset pin of the JESD RX module.

4) Send 0 to rx_reset pin of JESD RX module.

5) Write 0x2 to JESD RX AXI register 0x04 (fixed reset) to hold the JESD core in reset.

6) Program ADC registers.

7) Clear JESD core reset. After clearing reset, the GT lanes start seeing 0xBCBC characters.

Trigger Sysref

0 Kudos