JESD204B_PHY clock pins assigned incorrect FREQ_HZ value in 2018.1

[kinkeads]

I upgraded a working design from Vivado 2017.3 to Vivado 20181.   My block design contains a JESD204B_PHY core operating at 125MHz.  All the clock inputs to the JESD204B_PHY have a FREQ_HZ property of 125MHZ, but the output clock pins (rxout_clk and txout_clk) have a FREQ_HZ property set to 0.0.  

When I validate the block design, Vivado reports an mismatched clock frequency error between the JESD204B_PHY rxout_clk and the BUFG_GT it is driving.

[BD 41-238] Port/Pin property FREQ_HZ does not match between clk_wiz_0/clk_in1(125000000) and util_ds_bug_0/BUF_GT_O(0.000)

Again, this design passed validation in Vivado 2017.3, since the rxout_clk and txout_clk pins have their FREQ_HZ property correctly set to 125MHz. 

Why does Vivado 2018.1 not assign the correct frequency to the rxout_clk and txout_clk pins on the JESD204B_PHY?

[drjohnsmith]

how did you update the core ?

I thought there were some big design changes ,

  have hunt through AR for 18.1 and 18.2 

[kinkeads]

I used the Reports > Report IP Status  tool to upgrade all the IP.   I also tried deleting the IP and then re-adding it.

The 2018.1 Vivado Release Notes has this:

JESD204 PHY (4.0)

* Version 4.0 (Rev. 2)

* Bug Fix: Corrected an issue where numerical rounding could occasionally result in incorrect frequency being set on tx/rxoutclk ports in IP integrator.

Perhaps the bug fix made it worse.

[kinkeads · Accepted solution]

Xilinx tech support found a work-around.   When configuring the JESD204_PHY, the Line Rate parameter for the transmitter and receiver must be a floating point value, not an integer.   Note, this issue exist in 2018.1 and 2018.2.