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nml_555
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Registered: ‎12-07-2018

JESD204B Repeatable Latency

I have a design using JESD204B subclass 1, with 4 lanes, with a F*K = 32. 

I have some questions regarding the "Achieving Repeatable Latency" section in product guide PG066. 

1) How repeatable should the values be in the BUFFER ADJUST registers? From reset+initialization cycle to cycle, I am able to see values that jump between 0 and 32. The lanes are generally within 0x4 of one another.

2) I have attempted to follow the Achieving Repeatable Latency instructions, but no combination of SYSREF DELAY or BUFFER DELAY (Reg 0x30) result in any sort of repeatable results.

3) Bumping K to 32 resulting in F*K = 64 yields similar results. From cycle to cycle, BUFFER ADJUST registers return values between 0 and 64.

 

Assistance with better understanding this symptom and achieving repeatable latency is appreciated. 

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nathanx
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Registered: ‎08-01-2007

What's your clocking scheme, do you follow the clocking scheme on PG066? If you do not follow the clocking scheme on user guide, then the repeatable latency can not be guaranteed.

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nml_555
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Registered: ‎12-07-2018

Hi @nathanx , yes we are following the clocking scheme in figure 3-3 on PG066. SYSREF is a differential signal going to an IBUFDS.

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nathanx
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Registered: ‎08-01-2007

Then look at the "RX End to End Latency" on PG066 page 65 to page 69 to check if your F*K setting is good.

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nml_555
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Registered: ‎12-07-2018

We have looked through that page and our F*K settings are good.

After making some more adjustments, we found that if we run in SYSREF continuous mode, we seem to have a repeatable 0x0 to 0x4 buffer adjust which we can repeatedly adjust into the safe timing window. But running in n-shot mode still yields inconsistent results. I don't know if this is to be expected or not. For now, we are continuing to try to get our system working properly in continuous mode to achieve repeatable latency.

However, in continuous mode, I see the following errors that I do not see in n-shot:

  • Link status register 0x1C does not report any errors
  • Each lane shows thousands of not-in-table and disparity errors in the link error count registers (0x824, 0x864, etc), incrementing between resets.
  • We currently are not asserting bit 8 of register 0x34, FYI
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nathanx
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Registered: ‎08-01-2007

not-in-table and disparity errors are definitely GT errors. Is the link clean? Have you tried to observe eye diagram? Is it good? Is power supply clean?

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