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Visitor dbm2019
Visitor
183 Views
Registered: ‎07-17-2019

JESD204B always in reset state

I use hmc7044 clock chip to provide reference clock and sysref clock for ku115 FPGA, and receive data from adc9208.

The clock for ADC is 2949.12MHz, the reference clock for jesd204b IP is 737.28MHz, the global clock is 368.64MHz, and the sysref clock is 2.88mhz. The output level of clock from HMC7044 is LVDS.

At the sender, the PLL of ADC9208 has been locked and LMFC has been generated.

However, at the receiving end, I read the registers of jesd204b IP of FPGA, and found that this IP core has been always in reset state, and indicated that sysref signal was not caught. 

What may be the cause?

IP.png
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2 Replies
Moderator
Moderator
112 Views
Registered: ‎08-01-2007

回复: JESD204B always in reset state

Does GT complete intialization? Is GT resetdone high? Also probe all the clocks and reset of JESD IP.

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Adventurer
Adventurer
97 Views
Registered: ‎04-04-2018

回复: JESD204B always in reset state

Check the level of your reset signals. It is easy to mis-connect these especially on IP that have resets with different levels.
Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com
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