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Contributor
Contributor
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Registered: ‎03-16-2018

JESD204B block design with and without PHY

When I generate a block design that instantiates the JESD204B RX core and select the "Include Shared Logic in core" option the core will never come out of reset (reg 0x4 = 0x1).  When I select "Include Shared Logic in example design" and provide a JESD204B PHY block then the core will come out of reset.  I had the same behavior when the tx_reset_gt and tx_sys_reset where left unconnected and the rtl showed them hard coded to '0'.  

Should the JESD204B receiver core work alone or must the PHY always be included?

Vivado 2019.2

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Moderator
Moderator
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Registered: ‎08-01-2007

The PHY is required, the full JESD204 solution is made up of JESD204 IP core + JESD204 PHY. 

As for the difference between "Include Shared Logic in example design" and "Include Shared Logic in core", have a look at PG066.

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