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jtanko12
Visitor
Visitor
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Registered: ‎10-04-2012

JESD204B checksum

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Hello,

Can please someone tell me what checksum is sent over the lane during ILAS
from the JESD204 Tx? I am using JESD204 (7.2)

The Rx side is a DAC (AD9152) that expects the checksum as:

"lower eight bits of the sum of the following fields: DID, BID, LID,
SCR, L - 1, F - 1, K - 1, M - 1, N - 1, SUBCLASSV, NP - 1,
JESDV, S - 1, and HD"

OR

the sum of some register values on the DAC related to the JESD configuration.

Thanks a lot,

Jakab

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jlarkin
Xilinx Employee
Xilinx Employee
1,144 Views
Registered: ‎08-10-2007

The JESD204B spec defines the checksum (FCHK) as the modulus 256 of the sum of Configuration link parameters: BID, CF, CS, DID, F, HD, JESDV, K, L, LID, M, N, N', PHADJ, S, SCR, SUBCLASSV

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jlarkin
Xilinx Employee
Xilinx Employee
1,145 Views
Registered: ‎08-10-2007

The JESD204B spec defines the checksum (FCHK) as the modulus 256 of the sum of Configuration link parameters: BID, CF, CS, DID, F, HD, JESDV, K, L, LID, M, N, N', PHADJ, S, SCR, SUBCLASSV

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intriple2018
Observer
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Registered: ‎07-02-2018

Hi, how can I obtain the DID/BID/JESDV and LID from Xilinx JESD IP? The Datasheet Says its located in ILA0->ILA3 Registers, however these registers are not readable nor writeable for TX. I am trying to establish link with AD9172 DAC.

Thanks

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jlarkin
Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2007

These values are in ILA Config Register 3, and if you look at the register map in PG066, you can see that this register is R/W for TX.  Look at ILA Config Register 3 for more details about what values are R, W, or R/W.

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intriple2018
Observer
Observer
1,056 Views
Registered: ‎07-02-2018

Thank you,

That was definitely my fault.

For some reason, I thought the ILA3 is not readable.

Seems to be OK according to the Datasheet.

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jlarkin
Xilinx Employee
Xilinx Employee
1,048 Views
Registered: ‎08-10-2007

Excellent, I'm glad you found that information useful.

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