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apogeedbkxilinx
Adventurer
Adventurer
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Registered: ‎04-02-2010

JESD204B clocks from MMCMs

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AR#71575 (https://www.xilinx.com/support/answers/71575.html) describes how to connect JESD204 cores for synchronization of ADCs.  Will this setup synchronize properly if I generate core_clk and sysref from an MMCMs driven by one of the Refclks?

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trevorr
Xilinx Employee
Xilinx Employee
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Registered: ‎09-09-2020

Hi @apogeedbkxilinx ,

 

As long as you can meet the timing requirements of the core_clk and sysref signals (as described in PG242) this should work.

https://www.xilinx.com/support/documentation/ip_documentation/jesd204c/v4_2/pg242-jesd204c.pdf 

 

However, we recommend using an external device for this operation as relying on the internal MMCMs can introduce unwanted latency.

 

I hope this information helps, and please let me know if you have any further questions. 

 

Regards, 

 

Trevor Rishavy

Xilinx Product Application Engineer

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trevorr
Xilinx Employee
Xilinx Employee
226 Views
Registered: ‎09-09-2020

Hi @apogeedbkxilinx ,

 

As long as you can meet the timing requirements of the core_clk and sysref signals (as described in PG242) this should work.

https://www.xilinx.com/support/documentation/ip_documentation/jesd204c/v4_2/pg242-jesd204c.pdf 

 

However, we recommend using an external device for this operation as relying on the internal MMCMs can introduce unwanted latency.

 

I hope this information helps, and please let me know if you have any further questions. 

 

Regards, 

 

Trevor Rishavy

Xilinx Product Application Engineer

View solution in original post