10-16-2020 12:33 PM
I'm currently trying to interface an ADC34j45EVM board with a ZCU106 using the JESD204 IPs, and having trouble obtaining SYNC. I'm currently trying to use the ADC in 20x mode:
The design appears to go through CGS and assert SYNC, but is very unstable, and frequently deasserts SYNC (such as in the images jesd_sync_problem.png and jesd_sync_problem_2.png attached)
The block design is somewhat convoluted at this point, but attached are the configurations for the JESD204 PHY IP and the JESD204 IP.
The clocking scheme used tries to follow PG066: the 320 MHz GTX_CLK signal from the FMC passes through a IBUFDSGTE, whose IBUF_OUT pin feeds the cpll_refclk pin of the JESD204 PHY block. The IBUF_DS_ODIV2 output (which outputs a 320 MHz clock, and is not used to divide the incoming clock) goes to a BUFG_GT, whose CE pin is driven by the gt_powergood signal from the JESD204 PHY, and which is configured to divide the clock by 4, obtaining a 80 MHz clock. This 80 MHz clock drives the drpclk, rx_core_clk and tx_core_clk (not sure if this is needed) pins from the JESD204 PHY IP, as well as the rx_core_clk pin from the JESD204 IP.
There is also a microblaze implemented in the design, which reads/writes the registers of the JESD204 PHY IP and the JESD204 IP. The code sets some registers (octets per frame, frames per multiframe, subclass), waits for pll lock and the first sync, and prints some debugging information through a serial console (attached as mb_jesd_serial_out.txt).
The ADC34j45EVM board is configured through SPI, based on the Texas Instruments provided config. file.
Is this configuration valid? I'm suspecting that the x20 mode of operation in the ADC is incompatible with the Xilinx IP cores, since they only operate in x40 (I was trying to get both systems to communicate, with the assumption that somehow JESD204 would allow it). Can anyone confirm this, or point out possible mistakes?
10-30-2020 04:03 AM
Hi @lb_fiber ,
Once in SYNC, there are 3 main reasons a system may fall out of sync / request a resync:
1) CGS is lost on any lane
2) incorrect transition from 0xBC to the start of ILA is detected
3) Misalignment in received data is detected (alignment codes in data detected at unexpected positions)
A resync will be triggered when 8 successive multiframe alignment characters are detected in unexpected places (not at end of multiframe)