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Registered: ‎05-08-2018

JESD204B post_synthesis simulation

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I am  developing a project with the JESD204B as RX  to develop an interface from an ADC-Converter to an Virtex Ultrascale+ FPGA.

I already got the project running in the simulation mode and sucessfully established a link with the complementary JESD204 Core instaniated as TX in the testbench and as RX in the real design. But in the Post-Synthesis Simulation the link doesnt work. the JESD204B TX is not instaniated in the post synthesis simulation at all. The core is supplied by an differnetial clk which is the same who supplies the RX core. the RX core is sucessfully synthesizable and in the behavioral simulation mode the whole TX-RX works correctly.

 

How is it possible to achieve a full post-synthesis(implmentation) simulation of this project or with the JESD204B IP core in general ?

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Registered: ‎05-08-2018

Hi

 

First thanks for your kind reply. The log file says that the Jesd204B IP-Core is not instantiated because it has no binding entity.

I am instantiating the TX core in the testbench to emulate the TX which is realized on the AD-Converetr chip in reality.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @michael_filkorn,

 

do you by chance have several simulation runs setup?

If you just have one run the simulation testbench should actually not change between behavioural and post-synthesis simulation and the TX should be still instantiated in there.

What is the simulation logfile saying?

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Registered: ‎05-08-2018

Hi

 

First thanks for your kind reply. The log file says that the Jesd204B IP-Core is not instantiated because it has no binding entity.

I am instantiating the TX core in the testbench to emulate the TX which is realized on the AD-Converetr chip in reality.

View solution in original post

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