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Registered: ‎04-12-2019

JESD204C PHY IP

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Hello,

From PG198, registers (0xA0 & 0xC0) are read-only for RXPLL & TXPLL respectively, and set as QPLL1. Is there a way to use QPLL0? I am using UltraScale+ (xcvu9p).

Thanks,

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Registered: ‎04-12-2019

Now I have correct TXOUTCLK/RXOUTCLK after QPLL0 being locked. This issue has been resolved by adding some reset registers. Let me close this thread.

Thanks,

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Registered: ‎08-01-2007

JESD204 PHY IP GUI allows the user to select PLL type.

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Registered: ‎04-12-2019

I was able to confirm QPLL0 lock after reconfigiring 204C IP. However, I don't see "txoutclk" from JESD204C PHY. "txoutclk" goes to BUFG_GT, and I don't see a clock source from the output of BUFG_GT. From Figure 3-30, there is TXOUTCLKSEL, but I don't see this option from generated IP. Where can I set the value for TXOUTCLKSEL?

 

Thanks,

Figure_3_30.PNG
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202 Views
Registered: ‎04-12-2019

Now I have correct TXOUTCLK/RXOUTCLK after QPLL0 being locked. This issue has been resolved by adding some reset registers. Let me close this thread.

Thanks,

View solution in original post

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