cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Participant
Participant
573 Views
Registered: ‎05-10-2017

Latency through clock boundaries in JESD204B Subclass 2 a.k.a. GTP recovered clock to refclk to coreclk in artix 7

Hi,

I have JESD204B RX IP in my Artix 7 design.  The link configuration and Artix 7 requirements need me to keep the coreclk and refclk separate.  In the Basic Generic Clocking Schemes of the PG066 October 4, 2017, I see that separating the coreclk and refclk this way allows us to make the refclk independent of the coreclk. 

How is the deterministic latency maintained if the coreclk is separate from the recovered clock?  My confusion stems from the fact that in JESD204B Subclass 2, the SYNC~ signal from the RX core is provided to the transmitter.  I am assuming that the SYNC~ is generated synchronous to the coreclk from the core.  But according tot the JESD204B protocol, the SYNC~ is generated after code group synchronization occurs, this should occur in the recovered clock domain.  Then isn't there an uncertainty to go from the recovered clock to the coreclk domain?

Can someone please shed light on how the uncertainty in the clock domain crossings is handled in the JESD204B IP?

Thank you. 

Best regards,

Sanjay

0 Kudos
8 Replies
Highlighted
Participant
Participant
513 Views
Registered: ‎05-10-2017

Xilinx? Anyone?
0 Kudos
Highlighted
Moderator
Moderator
490 Views
Registered: ‎01-10-2019

Hi @shparekh ,

Please refer  PG066 page no 59 for understanding the functionality of deterministic latency .

Thanks,
Rahul Khatri
---------------------------------------------------------------------------------
Please Kudo or Accept as a solution, If this Post helped you.
---------------------------------------------------------------------------------
0 Kudos
Highlighted
Teacher
Teacher
483 Views
Registered: ‎07-09-2009

Its inherent in the JESD204B specification.

The data is sent from the ADC at a constant rate, and the data is received at the FPGA IP core output at a constant rate,

The trick is the start up sequence of JESD204B,
this is used to pre fill the fifos in the loop such that they are never over flow or under flow, and then to monitor this.

Its good old fashioned Que theory ,


<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Participant
Participant
446 Views
Registered: ‎05-10-2017

Thank you.

Can we please dig deeper?  I am looking at the gtp xcvr guide pg146 fig 4-18

The guide says - One of these clocks can be selected -

  1. RXOUTCLKPMA  - recovered clk
  2. RXOUTCLKPCS - not recommended
  3. RXPLLREFCLK_DIV1 - derived from the reference clock in the receiver.
  4. RXPLLREFCLK_DIV2

Which clock is selected in the JESD204B RX to drive to the fabric?  JESD204B sc2 deterministic latency relies on the align characters, so it needs to operate in the PCS block of the transceivers.  So what is the relationship between the recovered clk in the xcvr block and the coreclk and refclk of the JESD ip? 

Thank you.

Best regards,

Sanjay        

 

0 Kudos
Highlighted
Moderator
Moderator
404 Views
Registered: ‎01-10-2019

Hi @shparekh ,

RXOUTCLKPMA  clock is used as a RXOUTCLK.

Thanks,
Rahul Khatri
---------------------------------------------------------------------------------
Please Kudo or Accept as a solution, If this Post helped you.
---------------------------------------------------------------------------------
0 Kudos
Highlighted
Participant
Participant
361 Views
Registered: ‎05-10-2017

What is the relationship of RXCLKOUTPMA to CORECLK of the core?  My understanding is that they are asynchrnous, so how is latency uncertainty removed?

0 Kudos
Highlighted
Teacher
Teacher
355 Views
Registered: ‎07-09-2009


Its good old fashioned Que theory ,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Moderator
Moderator
316 Views
Registered: ‎08-01-2007

If you want to get a deterministic latency, you need to follow the clock scheme Figure 3‐1 or Figure 3‐2 on PG066 October 4, 2017. The other clock scheme can not ensure the deterministic latency.

0 Kudos