LogiCoore IP FIFO: Clock Constraint

[zofre_rauhut]

Hi,

a very simple question, but I can't find a solution:

during synthesis and place&route every- time I got the critical warning that no clock-constraint is present for the clock-inputs of he FIFO => where can I edit the clock-constraint for the FIFO?

Thanks

Best Regards

Bodo

[gszakacs]

Can you post the actual warning?  Normally clocks are constrained at the top level of the design,

so the only additional "constraint" you need for a FIFO is the clock ratio between read and write

clocks, and then only if your core uses the built-in FIFO logic.

[zofre_rauhut]

Hi,

attached you will find the actual warnings,

Best regards

Bodo

[ckarman · Accepted solution]

The core clock constraint is sourced by the .xci file automatically. If you need to edit the constraints (which seems you do), you can find the constraints at:

<project_directory>/<project>_srcs/sources_1/ip/<core_name>/<core_name>/<core_name>_*.xdc.

There will be three .xdc files (depending on your configuration).

It seems that you just need to issue a "create_clock" constraint on the clk source nets.

Chris

[balkris]

I would recommend to use latest version of core . there is few changes in latest version specially on constraint side for better performance