cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
zofre_rauhut
Observer
Observer
11,023 Views
Registered: ‎03-20-2013

LogiCoore IP FIFO: Clock Constraint

Jump to solution

Hi,

a very simple question, but I can't find a solution:

during synthesis and place&route every- time I got the critical warning that no clock-constraint is present for the clock-inputs of he FIFO => where can I edit the clock-constraint for the FIFO?

 

Thanks

Best Regards

Bodo

 

0 Kudos
1 Solution

Accepted Solutions
ckarman
Xilinx Employee
Xilinx Employee
17,851 Views
Registered: ‎06-01-2011

The core clock constraint is sourced by the .xci file automatically. If you need to edit the constraints (which seems you do), you can find the constraints at:

 

<project_directory>/<project>_srcs/sources_1/ip/<core_name>/<core_name>/<core_name>_*.xdc.

There will be three .xdc files (depending on your configuration).

 

It seems that you just need to issue a "create_clock" constraint on the clk source nets.

 

Chris

View solution in original post

0 Kudos
4 Replies
gszakacs
Professor
Professor
11,014 Views
Registered: ‎08-14-2007

Can you post the actual warning?  Normally clocks are constrained at the top level of the design,

so the only additional "constraint" you need for a FIFO is the clock ratio between read and write

clocks, and then only if your core uses the built-in FIFO logic.

-- Gabor
0 Kudos
zofre_rauhut
Observer
Observer
11,010 Views
Registered: ‎03-20-2013

Hi,

attached you will find the actual warnings,

Best regards

Bodo

Synthesis_Implementation_critical_warnings.png
0 Kudos
ckarman
Xilinx Employee
Xilinx Employee
17,852 Views
Registered: ‎06-01-2011

The core clock constraint is sourced by the .xci file automatically. If you need to edit the constraints (which seems you do), you can find the constraints at:

 

<project_directory>/<project>_srcs/sources_1/ip/<core_name>/<core_name>/<core_name>_*.xdc.

There will be three .xdc files (depending on your configuration).

 

It seems that you just need to issue a "create_clock" constraint on the clk source nets.

 

Chris

View solution in original post

0 Kudos
balkris
Xilinx Employee
Xilinx Employee
10,786 Views
Registered: ‎08-01-2008
I would recommend to use latest version of core . there is few changes in latest version specially on constraint side for better performance
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos