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Learn
Adventurer
Adventurer
329 Views
Registered: ‎09-28-2020

MIG Controller

MIG IP with AXI4 interface ,Memory controller as a reordering logic, to re-order the request sent is this option  is this option telling that IP can support out of order , outstanding transactions & data interleaving for axi interface.

This reordering logic  can accept how many requests, is their any limitation on number on requesting sent to it.

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@Learn ,

I'd be surprised if the MIG controller did any reordering.  It wouldn't be to its advantage to do so complexity wise.

I would expect some adjustments between read and write channels, but not within read or write channels.

Dan

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Learn
Adventurer
Adventurer
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Registered: ‎09-28-2020

Hi Dan,

Thanks for the reply.     

Will this MIG IP with axi interface support outstanding transaction, out of order transaction,data interleaving? If it supports how?

 

I understood the reordering logic as

Controller reordering is suppose we have 3 requests send 1st request for row0 2nd request for row1 3rd request is for row0 then controller sends 1st request and then 3rd request because it will save precharge and serve the request faster and then 2 nd request. For this to happen user axi Interface would had sent requests without waiting for earlier transaction to complete as we will get response of 3rd request it as to support out of order transaction for different cases we may expect data interleaving also

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dgisselq
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Scholar
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Registered: ‎05-21-2015

@Learn ,

I'm not the expert on the internal functions of the MIG.  If you generate a MIG controller, you'll find most of the logic available to you.  Feel free to inspect it and learn what you can.

I can comment on my own DDR3 controller, and ... it didn't do reordering at that level.  In general, it wasn't to my advantage to do so.

You are welcome to build yours however you see fit.

Dan

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dgisselq
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Scholar
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Registered: ‎05-21-2015

@Learn ,

I should point something out here ... it takes at least a clock cycle to reorder two (or more) operands.  If the delay, without reordering, is only a clock cycle--then reordering really isn't worth it at all.

Also, if I recall how Xilinx's MIG is built, there's a protocol conversion that takes place prior to issuing requests to the memory.  After that protocol conversion, I don't recall any ID information being left.  In other words, I don't think the MIG does any of the reordering you are discussing.

Dan

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Learn
Adventurer
Adventurer
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Registered: ‎09-28-2020

Hi Dan, Thanks for the reply

If reordering is not used then we need to serve all requests in order right. Their will be no out of order transaction, multiple transactions and data interleaving one request as to wait for the earlier request to complete.

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dgisselq
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Scholar
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Registered: ‎05-21-2015

@Learn ,

That's mostly true.  You still need to decide how to arbitrate between read and write requests.

Dan

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