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Adventurer
Adventurer
242 Views
Registered: ‎09-28-2020

MIG IP - Addressing width

Hi,

In address width Calculation we have

For DDR3: C_S_AXI_ADDR_WIDTH = log2(RANKS) + ROW_WIDTH +COL_WIDTH + BANK_WIDTH +log2(PAYLOAD_WIDTH) – 3

as in AXI Addressing it is mentioned that EX , if payload load is 16 then log2(16)-3=1 , these one bit will be ignored and masked then, why in bit width calculation we have log2(PAYLOAD_WIDTH) – 3 , as this term is telling which bits are ignored and masked we can ignore this right.

then  C_S_AXI_ADDR_WIDTH = log2(RANKS) + ROW_WIDTH +COL_WIDTH + BANK_WIDTH

this ranks ,row_width, col_width, bank_width we be able to give the address width right

is my understanding correct,

Thanks in advance

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dgisselq
Scholar
Scholar
216 Views
Registered: ‎05-21-2015

@Learn ,

> Is my understanding correct?

Not quite.  The C_AXI_ADDR_WIDTH is the width required to access an octet (8-bits) of information.  It should be the log, based 2, of the size of your SDRAM--independent of any row, column, or bank address widths.  That mapping you'll have to do yourself.

Dan

 

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