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Visitor
Visitor
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Registered: ‎08-21-2019

MMCM i/p and o/p clocks have phase unaligned

Hi,

I had generated one MMCM using VIVADO, with i/p clock as 135M and o/p clocks are as 270M, 135M and 25M, the phase degree of 135M(i/p) and 270M(o/p) is zero.

After sometime the i/p clock stops, which results in "lock" going low after one PFD clock cycle, so i deasset the reset of the MMCM, and once clock restarts again, the reset is asserted almost around 6 clock cycle later w.r.t i/p clock of the MMCM in order to get the lock again and to ensure that their is no phase violations. However lock is coming after some delay, but the phase relation between 135M(i/p) and 270M(o/p) is violating.

Why this phase violation happening??

Thanks,

Monesh

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614 Views
Registered: ‎01-22-2015

@mmonesh 

Have you setup the Clocking Wizard to have Phase Alignment (ref page 35 of document PG065) between input and output clocks? 
phase_alignment.jpg 

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Teacher
Teacher
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Registered: ‎07-09-2009

You dont say what your device is , that might help.

There are various reset requirements on the MMCM depending upon the family. in particular some of the reset times have to be quiet long , especially if clock input is "changed" ,

There are on some parts that the MMCM must be held in reset whilst t input is changed !!

Three should be a clock doc for your chip,


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Visitor
Visitor
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Registered: ‎08-21-2019

markg@prosensing.com 

Yes the option of phase alignment is set.

Initially the clock is phase aligned but after some time the phase violation happens.

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Visitor
Visitor
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Registered: ‎08-21-2019

@drjohnsmith 

I am using VCU118 board.

Actually i had designed one logic in which once the clock stops and lock goes low, the reset is desasserted, so during the time when their is no clock i/p the MMCM is in reset, and once the clock start again the counter present in the logic count for 6 clock cycles and after that the reset is asserted.

So should i keep mmcm in reset for some more time??

But once all the above steps are completed the lock comes, the clocks are phase aligned, and actual phase violation happens after 50us, why is it so?? The i/p clock is continuous now and their no change in the phase/frequency of the clock.

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Hi @mmonesh 

What is the status of CLKINSTOPPED and CLKFBSTOPPED outputs when the phase error occurs?

Thanks,
Vinay

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Visitor
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Registered: ‎08-21-2019

HIi @vuppala,

CLKINSTOPPED and CLKFBSTOPPED are zero throughout, irrespective of the time of the phase error.

Thanks,

Monesh

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Registered: ‎01-22-2015

@mmonesh 

     ....but the phase relation between 135M(i/p) and 270M(o/p) is violating.
How much phase error/violation are you seeing?  -and how are you routing the clocks out of the FPGA so that you can measure the phase error/violation?

Please note that MMCM outputs have error/resolution for phase settings as described on page 74 of UG472(v1.14) for 7-Series devices and on page 41 of UG572(v1.9) for UltraScale devices.

You can avoid some of the phase error associated with MMCM outputs by using BUFGCE_DIVs in parallel as described on page 119 of UG949(v2019.2).

Mark

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Visitor
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Registered: ‎08-21-2019

markg@prosensing.com 

Sorry for the late reply, as i was engaged in some other work. Actually i am seeing that, my i/p clock is not exactly 135M throughout, as it is coming from another phy module.

So when i generated the MMCM i gave i/p clock as 135M, but from phy it is coming 135.030, and after some time it suddenly changed to 134.924 for few cycles, and again comes to comes to 135.030.

But lock reamins 1.

Accordingly o/p is changing, but its not instantaneous obviously, i want to know how many cycles does MMCM takes to generate o/p based on its i/p clock, can we reduce to as low as possible??

what is the PPM range, or a predefined window for phase alignment for which lock goes down??it this configurable??

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Teacher
Teacher
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Registered: ‎07-09-2009

There is a data sheet number for how fast the input can change frequency for the mmcm , Me thinks that input clock is outside the specifications for the MMCM input !!

It used to be common for some "any clock " clock chips to do this n/m clock output , so many at one frequency , so many at another the average frequency then being correct. But that sort of clock is not good for a MMCM input.

The MMCM might be better in PLL mode, but I think your outside data sheet here.
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Registered: ‎01-22-2015

@mmonesh 

...i want to know how many cycles does MMCM takes to generate o/p based on its i/p clock, can we reduce to as low as possible??

As drjohnsmith suggests, the maximum locking time for the Virtex UltraScale device on the VCU118 board can be found in device datasheet (DS923 in your case).  I find from DS923 that MMCM_TLOCKMAX is 100us.

However, since you say “lock reamins 1” then you are asking about the loop-bandwidth of the MMCM LOCKED circuitry.  I am not aware of direct adjustment for this loop-bandwidth.   However, I suspect that some settings in the Clocking Wizard (eg. Jitter Optimization) influence loop-bandwidth.

 

..what is the PPM range, or a predefined window for phase alignment for which lock goes down??it this configurable??

I cannot find specification of when exactly the MMCM looses LOCKED.  I suspect it is a complicated specification that involves both magnitude and time-duration of input-clock deviations from a desired value.  However, in DS923 we find the MMCM_FINJITTER specification of “ < 20% of clock input period or 1 ns Max” – and from this you might infer something about maximum-tolerated frequency-phase deviations on the input-clock.

Finally, you might try using the PLL to see (experimentally) whether it remains LOCKED for higher deviations of the input-clock than the MMCM.

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