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jhallen
Observer
Observer
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Registered: ‎03-23-2017

MUX on PLL/MMCM feedback input (7 series)

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Hello,

I have a design were we dynamically optionally want phase locking. With no phase locking, the MMCM should act as a frequency multiplier only.  With phase locking, the MMCM should match its output phase with feedback from an external pin.

When I used Vivado 2017.2, I could do this with a LUT-based MUX on the MMCM's feedback input.  When I don't want phase locking, I set the MUX to connect the clkfb_in pin to the clkfb_out pin, otherwise it connects the clkfb_in pin to a chip external pin.

But now with Vivado 2019.2, this is a DRC violation with this message: "[DRC REQP-1972] Feedback check for LUT: The MMCME2_ADV cell dds_pll/mmcm_adv_inst_i_1 has unsupported connectivity. The CLKFBIN pin of the MMCM is connected to the CLKFBOUT pin on the same cell through a LUT . This is unknown clocking topology and will likely result in an improper compensation setting. Please fix the design."

Is there any way to suppress this check? The design was working fine in 2017.2.  I should say that the DRC is otherwise reasonable- the LUT is certainly adding some random routing delay, but in this particular design it does not matter (the routing delay is a tiny fraction of the very low frequency we are running at, so the phase delay is OK).

Any other ideas on how to have a dynamically selectable phase locking?

This is an Artix-7 design.

Thanks,

Joe

 

 

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bruce_karaffa
Scholar
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Registered: ‎06-21-2017

Can you use a BUFGMUX_CTRL to select a feedback clock?

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bruce_karaffa
Scholar
Scholar
457 Views
Registered: ‎06-21-2017

Can you use a BUFGMUX_CTRL to select a feedback clock?

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jhallen
Observer
Observer
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Registered: ‎03-23-2017

Thanks, that did it!

However I do get a strange warning:

   [Power 33-230] Invalid input clock frequency for dds_fb_mux. Out of range!

(dds_fb_mux is the BUFGMUX).

Maybe the power analysis tool is unhappy for some reason?

Joe

 

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