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Observer
Observer
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Registered: ‎10-19-2018

Modify Subsystem IP in Block Diagram

In a previous post (here), I was recommended to edit an AXI 1G/2.5G Ethernet Subsystem (with Shared Logic in Core), in order to remove its GTXE2_COMMON instantiation. This is necessary because there is an encrypted IP in the my design with an Aurora8b10b instantiation, with Shared Logic in Core, and since both transceivers are in the same quad (bank 113 for VC707), both are trying to use the only GTXE2_COMMON available in the bank. It is useless to set the AXI 1G/2.5G Ethernet Subsystem as Shared Logic in Example Design, because I do not have acess to the Aurora8b10b signals so as to share GTXE2_COMMON between the transceivers.

Firstly a tried to manually generate a custom IP, with the HDL and XCI sources from the AXI 1G/2.5G Ethernet Subsystem in the block design. Unfortunately, when synthetizing, Vivado always re-generate the output products, and the HDLs are reseted to their original content.

In AR 57546 (https://www.xilinx.com/support/answers/57546.html), there is a tcl script which claims to automatically generates the IP definition of a Subsystem IP in Block Design. I am following the steps provided in the answer, sourcing the tcl, and the IP is generated as a helper core and is hidden by default. After selecting the "Hide and disable incompatible IP" option in IP Catalog, I was able to see the IP.

But when instantiating it in the block diagram, I get the following error:

ERROR: [BD 5-216] VLNV <xilinx.com:ip:ethernet_1_10_25g:2.2> is not supported for the current part.
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

I have also tried to open the IP in IP Packager. The 'unsupported part' error appears there:

ip pack.PNG

 

How to proceed? Thanks in advance!

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-27-2019

回复: Modify Subsystem IP in Block Diagram

Hi @dicler ,

From the error message, it seems that your part doesn't support the IP.

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Observer
Observer
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Registered: ‎10-19-2018

回复: Modify Subsystem IP in Block Diagram

Hi @yangc, My part actually supports the IP. My block design with only one GT interface AXI 1G/2.5G Ethernet Subsystem (without Aurora8b10b) works properly. The 'unsupported part' error is associated with the IP generated when running the AR#57546 script, so my guess is that the script somehow changed the IPs part properties.

I think the problem can be related with the error reported in AR#66392

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Observer
Observer
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Registered: ‎10-19-2018

回复: Modify Subsystem IP in Block Diagram

I managed to solve the 'unsupported part' error by uncommenting the following line in the 'make_static.tcl' script:

# ipx::check_integrity $i

By doing so, the process 'makeXciDefinition' returns an error when checking IP Integrity, the IP Package procedure does not finish and its window keeps opened, allowing user edition, so I could manually insert the part support library to Virtex7. Probably this could be made by some tcl command in 'make_static.tcl' script.

Unfortunately the script does not worked, by not sourcing all the IP subcores into it, as shown in the next image.

ip package.PNG

I manually added the xci subcore sources, but it does not worked on the block design, as shown below:

 

ip errors.PNG

Any help will be appreciated, thanks.

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