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bolzw
Observer
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Registered: ‎07-15-2019

Multilane Aurora 64/66b GT pins swap rules ?

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Hi,

I want to connect 2 FPGA using Aurora 64/66v IP: Duplex, 16 GTH @ 10Gbps.

To ease layout, I would like to be able to swap pins in this 16 GHT bus.

For example:

 - FPGA1(GTH0...GTH15) <=> FPGA2(GTH15...GTH0) (see attached image)

 - or more complicated, "random" connection FPGA1(GTH0) <=> FPGA2(GTH5), FPGA1(GTH1) <=> FPGA2(GTH8), ...

 

My initial feeling was that any connection was possible, then re-order was done by managing Word order on tx_data and rx_data.

But I never used Aurora IP, is there some protocol limitation which makes swap not possible ?

 

Thanks for your help.

 

 

Aurora_gth_pin_swap.png
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bolzw
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Registered: ‎07-15-2019

Hi,

I get a solution from my FAE.

So, it is "easy" and feasible to swap lanes, you just have to edit IP automatic constrains to change pin order.

There is a very good power point from Xilinx your FAE can share, "Interleken Lane Reversal.pptx" which can be applied for any IP based on XCVR as Aurora 64/66 for me.

View solution in original post

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bolzw
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Registered: ‎07-15-2019

I still did not find any rule or statement about how Aurora lanes (GTH) are mapped to s_axi_tx_tdata and s_axi_rx_tdata bus.

Any confirmation that lane swapping can be achieved and original data retrieved just by re ordering rx bus would be helpful.

Thanks in advance.

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bolzw
Observer
Observer
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Registered: ‎07-15-2019

Hi,

I get a solution from my FAE.

So, it is "easy" and feasible to swap lanes, you just have to edit IP automatic constrains to change pin order.

There is a very good power point from Xilinx your FAE can share, "Interleken Lane Reversal.pptx" which can be applied for any IP based on XCVR as Aurora 64/66 for me.

View solution in original post

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