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Visitor xapeker2
Visitor
332 Views
Registered: ‎02-22-2019

Multiple JESD204B Phy blocks, clock sharing

Hi,

I want to use two lanes (DA0, DB0) of one ADC on a KU060. Due to PCB routing they are connected to CHANNEL_X1Y11 and CHANNEL_X1Y15. Refclk is connected to COMMON_X1Y2. Those are adjacent quads so clock distribution should work. As far as I understand I need two JESD204B Phy blocks because the lanes are no neighbors.

Refclk is connected via buf_gthe3 to qpll0_refclk and common0_qpll0_out of one phy goes to common0_qpll0_in.

In implementation I get the following error

[Place 30-510] Unroutable Placement! A GTHE_COMMON / GTHE_CHANNEL clock component pair is not placed in a routable site pair. The GTHE_COMMON component can use the dedicated path between the GTHE_COMMON and the GTHE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_inst/jesd204_phy_0/inst/jesd204_phy_gt_common_0_i/design_1_jesd204_phy_0_0_gt_common_i/common_inst/common0_qpll0_clk_out] >

	design_inst/jesd204_phy_0/inst/jesd204_phy_gt_common_0_i/design_1_jesd204_phy_0_0_gt_common_i/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST (GTHE3_COMMON.QPLL0OUTCLK) is provisionally placed by clockplacer on GTHE3_COMMON_X1Y4
	 design_inst/jesd204_phy_0/inst/jesd204_phy_block_i/design_1_jesd204_phy_0_0_gt_i/inst/gen_gtwizard_gthe3_top.design_1_jesd204_phy_0_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[26].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.QPLL0CLK) is locked to GTHE3_CHANNEL_X1Y11
	 design_inst/jesd204_phy_1/inst/design_1_jesd204_phy_1_0_gt_i/inst/gen_gtwizard_gthe3_top.design_1_jesd204_phy_1_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[27].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.QPLL0CLK) is locked to GTHE3_CHANNEL_X1Y15

	The above error could possibly be related to other connected instances. Following is a list of 
	all the related clock rules and their respective instances.

	Clock Rule: rule_bufds_gthcommon_intelligent_pin
	Status: PASS 
	Rule Description: A BUFDS driving a GTHCommon must both be placed in the same or adjacent two clock
	regions (top/bottom)
	 design_inst/util_ds_buf_0/U0/USE_IBUFDS_GTE3.GEN_IBUFDS_GTE3[0].IBUFDS_GTE3_I (IBUFDS_GTE3.O) is locked to GTHE3_COMMON_X1Y2
	 and design_inst/jesd204_phy_0/inst/jesd204_phy_gt_common_0_i/design_1_jesd204_phy_0_0_gt_common_i/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST (GTHE3_COMMON.GTREFCLK00) is provisionally placed by clockplacer on GTHE3_COMMON_X1Y4

Somehow the the Common block is placed in the wrong clock region. Does anybody know how clock distribution work between multiple Phys?

Cheers

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7 Replies
325 Views
Registered: ‎07-23-2019

Re: Multiple JESD204B Phy blocks, clock sharing

 

Are you feeding that ref clock to somewhere else?

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Visitor xapeker2
Visitor
317 Views
Registered: ‎02-22-2019

Re: Multiple JESD204B Phy blocks, clock sharing

Hi, 

no, the refclk_p/n input pins are directly connected to the IBUFDS_GTE3 block and the buf output goes to qpll0_refclk of the first jesd204b_phy_0. The odiv2 port is open. 

The phy_0 output common0_qpll0_out and phy_1 input common0_qpll0_in are connected as well.

I tried to fix the COMMON location in the constraints file but I get almost the same error:

set_property LOC GTHE3_COMMON_X1Y2 [get_cells -hier -filter {name =~ design_inst/jesd204_phy_0/inst/jesd204_phy_gt_common_0_i/design_1_jesd204_phy_0_0_gt_common_i/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST}]

errror:

[Place 30-510] Unroutable Placement! A GTHE_COMMON / GTHE_CHANNEL clock component pair is not placed in a routable site pair. The GTHE_COMMON component can use the dedicated path between the GTHE_COMMON and the GTHE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_inst/jesd204_phy_0/inst/jesd204_phy_gt_common_0_i/design_1_jesd204_phy_0_0_gt_common_i/common_inst/common0_qpll0_clk_out] >

	design_inst/jesd204_phy_0/inst/jesd204_phy_gt_common_0_i/design_1_jesd204_phy_0_0_gt_common_i/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST (GTHE3_COMMON.QPLL0OUTCLK) is locked to GTHE3_COMMON_X1Y2
	 design_inst/jesd204_phy_0/inst/jesd204_phy_block_i/design_1_jesd204_phy_0_0_gt_i/inst/gen_gtwizard_gthe3_top.design_1_jesd204_phy_0_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[26].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.QPLL0CLK) is locked to GTHE3_CHANNEL_X1Y11
	 design_inst/jesd204_phy_1/inst/design_1_jesd204_phy_1_0_gt_i/inst/gen_gtwizard_gthe3_top.design_1_jesd204_phy_1_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[27].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.QPLL0CLK) is locked to GTHE3_CHANNEL_X1Y15

	The above error could possibly be related to other connected instances. Following is a list of 
	all the related clock rules and their respective instances.

	Clock Rule: rule_bufds_gthcommon_intelligent_pin
	Status: PASS 
	Rule Description: A BUFDS driving a GTHCommon must both be placed in the same or adjacent two clock
	regions (top/bottom)
	 design_inst/buf_gthe3/U0/USE_IBUFDS_GTE3.GEN_IBUFDS_GTE3[0].IBUFDS_GTE3_I (IBUFDS_GTE3.O) is locked to GTHE3_COMMON_X1Y2
	 and design_inst/jesd204_phy_0/inst/jesd204_phy_gt_common_0_i/design_1_jesd204_phy_0_0_gt_common_i/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST (GTHE3_COMMON.GTREFCLK00) is locked to GTHE3_COMMON_X1Y2

jesd204b_phy0 is "Include Shared Logic in core"

jesd204b_phy1 is "Include Shared Logic in example design"

Hope that helps.

Cheers

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Visitor xapeker2
Visitor
307 Views
Registered: ‎02-22-2019

Re: Multiple JESD204B Phy blocks, clock sharing

While I can't get a working solution with two phys, one for each lane, I found a workaround (lets call it a hack). Using one Phy with 5 lanes starting from X1Y11 and connecting only the gt0 and gt4 seems to work perfectly.

I would not consider this a solution, but for now it works. However I would still be interessted in a solution with southbound/northbound clock routing with multiple phys.

Cheers

0 Kudos
281 Views
Registered: ‎07-23-2019

Re: Multiple JESD204B Phy blocks, clock sharing

 

Nice you found a way to, at least, carry on... I've seen a few of these "temporary hacks" that ended up in production for years... at the end of the day, doing the thing is what matters. Not saying you shouldn't go to the bottom of it.

How did you deploy your transceivers? I have used the Transceiver Wizard sometimes

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Visitor xapeker2
Visitor
268 Views
Registered: ‎02-22-2019

Re: Multiple JESD204B Phy blocks, clock sharing

If I find the time, I will have a deeper look. Not sure that I understand your question, the tranceivers are setup and deployed by the JESD204B Phy IP core. From there the receivers are connected to inputs, the transmitters are kept unconnected.

0 Kudos
263 Views
Registered: ‎07-23-2019

Re: Multiple JESD204B Phy blocks, clock sharing

 

Yep, the question was what IP core did you use. You answered it.

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Visitor xapeker2
Visitor
140 Views
Registered: ‎02-22-2019

Re: Multiple JESD204B Phy blocks, clock sharing

Hi,

I still want to keep this issue open. I do not understand how I can use 16 lanes sourced from a single refclk. The JESD204 Phy supports just 12 lanes. Sooner or later multiple Phys have to be used. 

Cheers 

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