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ppouyan
Observer
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Registered: ‎09-06-2018

Native FIFO to AXI

Hi all,

I would like to interface the native FIFO with AXI interface (AXI-Lite).

Basically I want the ZYNQ PS to write into the ZYNQ PL by a FIFO in between and since I need some characteristics of native FIFO  I do not use the AXI Stream FIFO IP.

I have read this https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Making-a-AXI-to-native-Fifo/td-p/458342 but need more information.

I know that I need to create a native FIFO and write some VHDL myself that converts the native signals to AXI on the write side of the FIFO.

I have difficulty on connecting the native signals to AXI (which oneS connects to each other), could you give hint on that? 

 

PS2PL.png
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dpaul24
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Registered: ‎08-07-2014

@ppouyan,

I know that I need to create a native FIFO and write some VHDL myself that converts the native signals to AXI on the write side of the FIFO.

If you don't ask specific questions, it is difficult to give hints. What is the difficulty? Have you started writing the VHDL?

I would suggest you to generate an axi fifo and then write a glue logic that will convert the axi read side signals to native signals (for the PL side). In this way you are 1 module ahead in debugging your design. You would atleast know that the axi read data is correct and you have to improve your wrapper logic.

I don't know you level of competence, so you may want to go with your original idea.

 

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ppouyan
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Registered: ‎09-06-2018

Thank you @dpaul24 dpaul24

By interfacing the signals in VHDL I mean that for example in AXI FIFO architecture  the valid signal is connected to wr_en and ready signal is connected to full etc.

Since the AXI interface contains valid and ready signals in all 5 channels including Write Data, Write Address, Write Response, Read Data, Read Address (in total 5*2=10 signals) then i.e wr_en and full are connected to which valid and ready signals? 

Can you elaborate more how using the AXI-FIFO can reduce the debugg effort?

AXI FIFO.png
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dpaul24
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Registered: ‎08-07-2014

@ppouyan,

Since the AXI interface contains valid and ready signals in all 5 channels including Write Data, Write Address, Write Response, Read Data, Read Address (in total 5*2=10 signals) then i.e wr_en and full are connected to which valid and ready signals?

That is where you have to write your own logic. You have combine the AXIs and generate the NATIVEs. Similarly generate the AXI signals from the Native on the other direction.

e.g. for AXI to Native side signal translation-- for a axi write operation, whenever your glue logic has registered a valid address and valid write data, then on the following clock cycle you make the wr_en (belonging to the fifo native signal) high and present the signals to the FIFO native interface.

e.g. for a Native to AXI side signal translation--When the full signal is HIGH, it means that the FIFO (which is the axi slave here) cannot accept any more data. Then use this info to drive the *READY signal low, such that the AXI master cannot send any more data.

You have to study both the signalling schemes and see how how they fit to and translate with each other.

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