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Observer anushakodimela
Observer
342 Views
Registered: ‎02-14-2019

Native asynchronous FIFO Generator access contents

Hi I have used Fifo generator IP core (Native,Independednt Clock ,Block Ram,No reset,Data width 32 and depth 2048 words) screenshots of Fifo generator IP are attached.

I was successful in writing data into the fifo and viewing the data as soon as it is written from the dout.Transmitting the dout data using an USB-UART bridge is throwing a set of garbage values(screenshot attached) instead of the value written in the fifo.Baud rates from the vhdl design and terminal end are in sync.

Could some one tell me if I am on the right track in transmitting data to the PC and also answer the question below

1.How do I know if my native FIFO generator is writting entries one after the other (or) replacing the previously written entry?

 

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Scholar dpaul24
Scholar
336 Views
Registered: ‎08-07-2014

Re: Native asynchronous FIFO Generator access contents

@anushakodimela,

1.How do I know if my native FIFO generator is writting entries one after the other (or) replacing the previously written entry?

As I see it before taking the data to TeraTerm, I would do a simulation of the design. It would not take a lot of effort.

In the waveform I would keep an eye on the dout of the FIFO and observe whether the same data is being tx out bit by bit via the UART in the correct sequence or not.

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Observer anushakodimela
Observer
317 Views
Registered: ‎02-14-2019

Re: Native asynchronous FIFO Generator access contents

The simulation is done and the results look fine.But when the bit is programmed I get the terminal result as shown below.Attached simulation result of the Tx signal that is being transmitted 

usb_uart_working modeltxsignal.PNG
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